2 * (C) Copyright 2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/mx5x_pins.h>
28 #include <asm/arch/iomux.h>
29 #include <asm/errno.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/arch/crm_regs.h>
32 #include <asm/arch/clock.h>
35 #include <fsl_esdhc.h>
39 #include <usb/ehci-fsl.h>
41 #include <ipu_pixfmt.h>
43 #define MX51EVK_LCD_3V3 IMX_GPIO_NR(4, 9)
44 #define MX51EVK_LCD_5V IMX_GPIO_NR(4, 10)
45 #define MX51EVK_LCD_BACKLIGHT IMX_GPIO_NR(3, 4)
47 DECLARE_GLOBAL_DATA_PTR;
49 #ifdef CONFIG_FSL_ESDHC
50 struct fsl_esdhc_cfg esdhc_cfg[2] = {
51 {MMC_SDHC1_BASE_ADDR},
52 {MMC_SDHC2_BASE_ADDR},
58 /* dram_init must store complete ramsize in gd->ram_size */
59 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
64 u32 get_board_rev(void)
66 u32 rev = get_cpu_rev();
67 if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
68 rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
72 static void setup_iomux_uart(void)
74 unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
75 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
77 mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
78 mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
79 mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
80 mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
81 mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
82 mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
83 mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
84 mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
87 static void setup_iomux_fec(void)
90 mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
91 mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
94 mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
95 mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
98 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
99 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
102 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
103 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
106 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
107 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
110 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
111 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
114 mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
115 mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
118 mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
119 mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
122 mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
123 mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
126 mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
127 mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
130 mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
131 mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
134 mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
135 mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
138 mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
139 mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
142 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
143 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
146 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
147 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
150 mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
151 mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
154 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
155 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
158 mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
159 mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
162 #ifdef CONFIG_MXC_SPI
163 static void setup_iomux_spi(void)
165 /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
166 mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
167 mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
169 /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
170 mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
171 mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
173 /* de-select SS1 of instance: ecspi1. */
174 mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
175 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
177 /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
178 mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
179 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
181 /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
182 mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
183 mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
185 /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
186 mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
187 mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
191 #ifdef CONFIG_USB_EHCI_MX5
192 #define MX51EVK_USBH1_HUB_RST IOMUX_TO_GPIO(MX51_PIN_GPIO1_7) /* GPIO1_7 */
193 #define MX51EVK_USBH1_STP IOMUX_TO_GPIO(MX51_PIN_USBH1_STP) /* GPIO1_27 */
194 #define MX51EVK_USB_CLK_EN_B IOMUX_TO_GPIO(MX51_PIN_EIM_D18) /* GPIO2_1 */
195 #define MX51EVK_USB_PHY_RESET IOMUX_TO_GPIO(MX51_PIN_EIM_D21) /* GPIO2_5 */
197 #define USBH1_PAD (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | \
198 PAD_CTL_100K_PU | PAD_CTL_PUE_PULL | \
199 PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE)
200 #define GPIO_PAD (PAD_CTL_DRV_HIGH | PAD_CTL_PKE_ENABLE | \
202 #define NO_PAD (1 << 16)
204 static void setup_usb_h1(void)
206 setup_iomux_usb_h1();
208 /* GPIO_1_7 for USBH1 hub reset */
209 mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
210 mxc_iomux_set_pad(MX51_PIN_GPIO1_7, NO_PAD);
213 mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT1);
214 mxc_iomux_set_pad(MX51_PIN_EIM_D17, GPIO_PAD);
216 /* GPIO_2_5 for USB PHY reset */
217 mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT1);
218 mxc_iomux_set_pad(MX51_PIN_EIM_D21, GPIO_PAD);
221 int board_ehci_hcd_init(int port)
223 /* Set USBH1_STP to GPIO and toggle it */
224 mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_GPIO);
225 mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
227 gpio_direction_output(MX51EVK_USBH1_STP, 0);
228 gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
230 gpio_set_value(MX51EVK_USBH1_STP, 1);
232 /* Set back USBH1_STP to be function */
233 mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
234 mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
236 /* De-assert USB PHY RESETB */
237 gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
239 /* Drive USB_CLK_EN_B line low */
240 gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0);
243 gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0);
245 gpio_set_value(MX51EVK_USBH1_HUB_RST, 1);
250 static void power_init(void)
253 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
259 /* Write needed to Power Gate 2 register */
260 pmic_reg_read(p, REG_POWER_MISC, &val);
262 pmic_reg_write(p, REG_POWER_MISC, val);
264 /* Externally powered */
265 pmic_reg_read(p, REG_CHARGE, &val);
266 val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
267 pmic_reg_write(p, REG_CHARGE, val);
269 /* power up the system first */
270 pmic_reg_write(p, REG_POWER_MISC, PWUP);
272 /* Set core voltage to 1.1V */
273 pmic_reg_read(p, REG_SW_0, &val);
274 val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
275 pmic_reg_write(p, REG_SW_0, val);
277 /* Setup VCC (SW2) to 1.25 */
278 pmic_reg_read(p, REG_SW_1, &val);
279 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
280 pmic_reg_write(p, REG_SW_1, val);
282 /* Setup 1V2_DIG1 (SW3) to 1.25 */
283 pmic_reg_read(p, REG_SW_2, &val);
284 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
285 pmic_reg_write(p, REG_SW_2, val);
288 /* Raise the core frequency to 800MHz */
289 writel(0x0, &mxc_ccm->cacrr);
291 /* Set switchers in Auto in NORMAL mode & STANDBY mode */
292 /* Setup the switcher mode for SW1 & SW2*/
293 pmic_reg_read(p, REG_SW_4, &val);
294 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
295 (SWMODE_MASK << SWMODE2_SHIFT)));
296 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
297 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
298 pmic_reg_write(p, REG_SW_4, val);
300 /* Setup the switcher mode for SW3 & SW4 */
301 pmic_reg_read(p, REG_SW_5, &val);
302 val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
303 (SWMODE_MASK << SWMODE4_SHIFT)));
304 val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
305 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
306 pmic_reg_write(p, REG_SW_5, val);
308 /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
309 pmic_reg_read(p, REG_SETTING_0, &val);
310 val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
311 val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
312 pmic_reg_write(p, REG_SETTING_0, val);
314 /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
315 pmic_reg_read(p, REG_SETTING_1, &val);
316 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
317 val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
318 pmic_reg_write(p, REG_SETTING_1, val);
320 /* Configure VGEN3 and VCAM regulators to use external PNP */
321 val = VGEN3CONFIG | VCAMCONFIG;
322 pmic_reg_write(p, REG_MODE_1, val);
325 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
326 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
327 VVIDEOEN | VAUDIOEN | VSDEN;
328 pmic_reg_write(p, REG_MODE_1, val);
330 mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1);
331 gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
335 gpio_set_value(IMX_GPIO_NR(2, 14), 1);
338 #ifdef CONFIG_FSL_ESDHC
339 int board_mmc_getcd(struct mmc *mmc)
341 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
344 mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT1);
345 gpio_direction_input(IMX_GPIO_NR(1, 0));
346 mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
347 gpio_direction_input(IMX_GPIO_NR(1, 6));
349 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
350 ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
352 ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
357 int board_mmc_init(bd_t *bis)
362 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
363 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
365 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
369 mxc_request_iomux(MX51_PIN_SD1_CMD,
370 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
371 mxc_request_iomux(MX51_PIN_SD1_CLK,
372 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
373 mxc_request_iomux(MX51_PIN_SD1_DATA0,
374 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
375 mxc_request_iomux(MX51_PIN_SD1_DATA1,
376 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
377 mxc_request_iomux(MX51_PIN_SD1_DATA2,
378 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
379 mxc_request_iomux(MX51_PIN_SD1_DATA3,
380 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
381 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
382 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
383 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
385 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
386 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
387 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
388 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
390 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
391 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
392 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
393 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
395 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
396 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
397 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
398 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
400 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
401 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
402 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
403 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
405 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
406 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
407 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
408 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
410 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
411 mxc_request_iomux(MX51_PIN_GPIO1_0,
412 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
413 mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
415 mxc_request_iomux(MX51_PIN_GPIO1_1,
416 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
417 mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
421 mxc_request_iomux(MX51_PIN_SD2_CMD,
422 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
423 mxc_request_iomux(MX51_PIN_SD2_CLK,
424 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
425 mxc_request_iomux(MX51_PIN_SD2_DATA0,
427 mxc_request_iomux(MX51_PIN_SD2_DATA1,
429 mxc_request_iomux(MX51_PIN_SD2_DATA2,
431 mxc_request_iomux(MX51_PIN_SD2_DATA3,
433 mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
434 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
436 mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
437 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
439 mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
440 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
442 mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
443 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
445 mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
446 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
448 mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
449 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
451 mxc_request_iomux(MX51_PIN_SD2_CMD,
452 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
453 mxc_request_iomux(MX51_PIN_GPIO1_6,
454 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
455 mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
457 mxc_request_iomux(MX51_PIN_GPIO1_5,
458 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
459 mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
463 printf("Warning: you configured more ESDHC controller"
464 "(%d) as supported by the board(2)\n",
465 CONFIG_SYS_FSL_ESDHC_NUM);
468 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
474 static struct fb_videomode claa_wvga = {
475 .name = "CLAA07LC0ACW",
487 .vmode = FB_VMODE_NONINTERLACED
493 mxc_request_iomux(MX51_PIN_DI_GP4, IOMUX_CONFIG_ALT4);
495 /* Pad settings for MX51_PIN_DI2_DISP_CLK */
496 mxc_iomux_set_pad(MX51_PIN_DI2_DISP_CLK, PAD_CTL_HYS_NONE |
497 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
498 PAD_CTL_DRV_MAX | PAD_CTL_SRE_SLOW);
500 /* Turn on 3.3V voltage for LCD */
501 mxc_request_iomux(MX51_PIN_CSI2_D12, IOMUX_CONFIG_ALT3);
502 gpio_direction_output(MX51EVK_LCD_3V3, 1);
504 /* Turn on 5V voltage for LCD */
505 mxc_request_iomux(MX51_PIN_CSI2_D13, IOMUX_CONFIG_ALT3);
506 gpio_direction_output(MX51EVK_LCD_5V, 1);
508 /* Turn on GPIO backlight */
509 mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
510 mxc_iomux_set_input(MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
512 gpio_direction_output(MX51EVK_LCD_BACKLIGHT, 1);
515 void lcd_enable(void)
517 int ret = ipuv3_fb_init(&claa_wvga, 1, IPU_PIX_FMT_RGB565);
519 printf("LCD cannot be configured: %d\n", ret);
522 int board_early_init_f(void)
526 #ifdef CONFIG_USB_EHCI_MX5
536 /* address of boot parameters */
537 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
544 #ifdef CONFIG_BOARD_LATE_INIT
545 int board_late_init(void)
547 #ifdef CONFIG_MXC_SPI
557 * Do not overwrite the console
558 * Use always serial for U-Boot console
560 int overwrite_console(void)
567 puts("Board: MX51EVK\n");