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powerpc/85xx: Add networking support to P1023RDS
[u-boot] / board / freescale / mx51evk / mx51evk.c
1 /*
2  * (C) Copyright 2009 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22
23 #include <common.h>
24 #include <asm/io.h>
25 #include <asm/gpio.h>
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/mx5x_pins.h>
28 #include <asm/arch/iomux.h>
29 #include <asm/errno.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/arch/crm_regs.h>
32 #include <i2c.h>
33 #include <mmc.h>
34 #include <fsl_esdhc.h>
35 #include <fsl_pmic.h>
36 #include <mc13892.h>
37
38 DECLARE_GLOBAL_DATA_PTR;
39
40 static u32 system_rev;
41
42 #ifdef CONFIG_FSL_ESDHC
43 struct fsl_esdhc_cfg esdhc_cfg[2] = {
44         {MMC_SDHC1_BASE_ADDR, 1},
45         {MMC_SDHC2_BASE_ADDR, 1},
46 };
47 #endif
48
49 u32 get_board_rev(void)
50 {
51         return system_rev;
52 }
53
54 int dram_init(void)
55 {
56         /* dram_init must store complete ramsize in gd->ram_size */
57         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
58                                 PHYS_SDRAM_1_SIZE);
59         return 0;
60 }
61
62 static void setup_iomux_uart(void)
63 {
64         unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
65                         PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
66
67         mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
68         mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
69         mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
70         mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
71         mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
72         mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
73         mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
74         mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
75 }
76
77 static void setup_iomux_fec(void)
78 {
79         /*FEC_MDIO*/
80         mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
81         mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
82
83         /*FEC_MDC*/
84         mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
85         mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
86
87         /* FEC RDATA[3] */
88         mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
89         mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
90
91         /* FEC RDATA[2] */
92         mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
93         mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
94
95         /* FEC RDATA[1] */
96         mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
97         mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
98
99         /* FEC RDATA[0] */
100         mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
101         mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
102
103         /* FEC TDATA[3] */
104         mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
105         mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
106
107         /* FEC TDATA[2] */
108         mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
109         mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
110
111         /* FEC TDATA[1] */
112         mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
113         mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
114
115         /* FEC TDATA[0] */
116         mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
117         mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
118
119         /* FEC TX_EN */
120         mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
121         mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
122
123         /* FEC TX_ER */
124         mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
125         mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
126
127         /* FEC TX_CLK */
128         mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
129         mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
130
131         /* FEC TX_COL */
132         mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
133         mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
134
135         /* FEC RX_CLK */
136         mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
137         mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
138
139         /* FEC RX_CRS */
140         mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
141         mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
142
143         /* FEC RX_ER */
144         mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
145         mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
146
147         /* FEC RX_DV */
148         mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
149         mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
150 }
151
152 #ifdef CONFIG_MXC_SPI
153 static void setup_iomux_spi(void)
154 {
155         /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
156         mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
157         mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
158
159         /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
160         mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
161         mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
162
163         /* de-select SS1 of instance: ecspi1. */
164         mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
165         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
166
167         /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
168         mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
169         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
170
171         /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
172         mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
173         mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
174
175         /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
176         mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
177         mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
178 }
179 #endif
180
181 static void power_init(void)
182 {
183         unsigned int val;
184         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
185
186         /* Write needed to Power Gate 2 register */
187         val = pmic_reg_read(REG_POWER_MISC);
188         val &= ~PWGT2SPIEN;
189         pmic_reg_write(REG_POWER_MISC, val);
190
191         /* Externally powered */
192         val = pmic_reg_read(REG_CHARGE);
193         val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
194         pmic_reg_write(REG_CHARGE, val);
195
196         /* power up the system first */
197         pmic_reg_write(REG_POWER_MISC, PWUP);
198
199         /* Set core voltage to 1.1V */
200         val = pmic_reg_read(REG_SW_0);
201         val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
202         pmic_reg_write(REG_SW_0, val);
203
204         /* Setup VCC (SW2) to 1.25 */
205         val = pmic_reg_read(REG_SW_1);
206         val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
207         pmic_reg_write(REG_SW_1, val);
208
209         /* Setup 1V2_DIG1 (SW3) to 1.25 */
210         val = pmic_reg_read(REG_SW_2);
211         val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
212         pmic_reg_write(REG_SW_2, val);
213         udelay(50);
214
215         /* Raise the core frequency to 800MHz */
216         writel(0x0, &mxc_ccm->cacrr);
217
218         /* Set switchers in Auto in NORMAL mode & STANDBY mode */
219         /* Setup the switcher mode for SW1 & SW2*/
220         val = pmic_reg_read(REG_SW_4);
221         val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
222                 (SWMODE_MASK << SWMODE2_SHIFT)));
223         val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
224                 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
225         pmic_reg_write(REG_SW_4, val);
226
227         /* Setup the switcher mode for SW3 & SW4 */
228         val = pmic_reg_read(REG_SW_5);
229         val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
230                 (SWMODE_MASK << SWMODE4_SHIFT)));
231         val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
232                 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
233         pmic_reg_write(REG_SW_5, val);
234
235         /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
236         val = pmic_reg_read(REG_SETTING_0);
237         val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
238         val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
239         pmic_reg_write(REG_SETTING_0, val);
240
241         /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
242         val = pmic_reg_read(REG_SETTING_1);
243         val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
244         val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
245         pmic_reg_write(REG_SETTING_1, val);
246
247         /* Configure VGEN3 and VCAM regulators to use external PNP */
248         val = VGEN3CONFIG | VCAMCONFIG;
249         pmic_reg_write(REG_MODE_1, val);
250         udelay(200);
251
252         gpio_direction_output(46, 0);
253
254         /* Reset the ethernet controller over GPIO */
255         writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
256
257         /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
258         val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
259                 VVIDEOEN | VAUDIOEN  | VSDEN;
260         pmic_reg_write(REG_MODE_1, val);
261
262         udelay(500);
263
264         gpio_set_value(46, 1);
265 }
266
267 #ifdef CONFIG_FSL_ESDHC
268 int board_mmc_getcd(u8 *cd, struct mmc *mmc)
269 {
270         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
271
272         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
273                 *cd = gpio_get_value(0);
274         else
275                 *cd = gpio_get_value(6);
276
277         return 0;
278 }
279
280 int board_mmc_init(bd_t *bis)
281 {
282         u32 index;
283         s32 status = 0;
284
285         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
286                         index++) {
287                 switch (index) {
288                 case 0:
289                         mxc_request_iomux(MX51_PIN_SD1_CMD,
290                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
291                         mxc_request_iomux(MX51_PIN_SD1_CLK,
292                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
293                         mxc_request_iomux(MX51_PIN_SD1_DATA0,
294                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
295                         mxc_request_iomux(MX51_PIN_SD1_DATA1,
296                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
297                         mxc_request_iomux(MX51_PIN_SD1_DATA2,
298                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
299                         mxc_request_iomux(MX51_PIN_SD1_DATA3,
300                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
301                         mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
302                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
303                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
304                                 PAD_CTL_PUE_PULL |
305                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
306                         mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
307                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
308                                 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
309                                 PAD_CTL_PUE_PULL |
310                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
311                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
312                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
313                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
314                                 PAD_CTL_PUE_PULL |
315                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
316                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
317                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
318                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
319                                 PAD_CTL_PUE_PULL |
320                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
321                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
322                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
323                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
324                                 PAD_CTL_PUE_PULL |
325                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
326                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
327                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
328                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
329                                 PAD_CTL_PUE_PULL |
330                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
331                         mxc_request_iomux(MX51_PIN_GPIO1_0,
332                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
333                         mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
334                                 PAD_CTL_HYS_ENABLE);
335                         mxc_request_iomux(MX51_PIN_GPIO1_1,
336                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
337                         mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
338                                 PAD_CTL_HYS_ENABLE);
339                         break;
340                 case 1:
341                         mxc_request_iomux(MX51_PIN_SD2_CMD,
342                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
343                         mxc_request_iomux(MX51_PIN_SD2_CLK,
344                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
345                         mxc_request_iomux(MX51_PIN_SD2_DATA0,
346                                 IOMUX_CONFIG_ALT0);
347                         mxc_request_iomux(MX51_PIN_SD2_DATA1,
348                                 IOMUX_CONFIG_ALT0);
349                         mxc_request_iomux(MX51_PIN_SD2_DATA2,
350                                 IOMUX_CONFIG_ALT0);
351                         mxc_request_iomux(MX51_PIN_SD2_DATA3,
352                                 IOMUX_CONFIG_ALT0);
353                         mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
354                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
355                                 PAD_CTL_SRE_FAST);
356                         mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
357                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
358                                 PAD_CTL_SRE_FAST);
359                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
360                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
361                                 PAD_CTL_SRE_FAST);
362                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
363                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
364                                 PAD_CTL_SRE_FAST);
365                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
366                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
367                                 PAD_CTL_SRE_FAST);
368                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
369                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
370                                 PAD_CTL_SRE_FAST);
371                         mxc_request_iomux(MX51_PIN_SD2_CMD,
372                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
373                         mxc_request_iomux(MX51_PIN_GPIO1_6,
374                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
375                         mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
376                                 PAD_CTL_HYS_ENABLE);
377                         mxc_request_iomux(MX51_PIN_GPIO1_5,
378                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
379                         mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
380                                 PAD_CTL_HYS_ENABLE);
381                         break;
382                 default:
383                         printf("Warning: you configured more ESDHC controller"
384                                 "(%d) as supported by the board(2)\n",
385                                 CONFIG_SYS_FSL_ESDHC_NUM);
386                         return status;
387                 }
388                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
389         }
390         return status;
391 }
392 #endif
393
394 int board_early_init_f(void)
395 {
396         setup_iomux_uart();
397         setup_iomux_fec();
398
399         return 0;
400 }
401
402 int board_init(void)
403 {
404         system_rev = get_cpu_rev();
405
406         gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE;
407         /* address of boot parameters */
408         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
409
410         return 0;
411 }
412
413 #ifdef BOARD_LATE_INIT
414 int board_late_init(void)
415 {
416 #ifdef CONFIG_MXC_SPI
417         setup_iomux_spi();
418         power_init();
419 #endif
420         return 0;
421 }
422 #endif
423
424 int checkboard(void)
425 {
426         puts("Board: MX51EVK\n");
427
428         return 0;
429 }