2 * (C) Copyright 2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/mx5x_pins.h>
28 #include <asm/arch/iomux.h>
29 #include <asm/errno.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/arch/crm_regs.h>
34 #include <fsl_esdhc.h>
38 #include <usb/ehci-fsl.h>
40 #include <ipu_pixfmt.h>
42 #define MX51EVK_LCD_3V3 IMX_GPIO_NR(4, 9)
43 #define MX51EVK_LCD_5V IMX_GPIO_NR(4, 10)
44 #define MX51EVK_LCD_BACKLIGHT IMX_GPIO_NR(3, 4)
46 DECLARE_GLOBAL_DATA_PTR;
48 #ifdef CONFIG_FSL_ESDHC
49 struct fsl_esdhc_cfg esdhc_cfg[2] = {
50 {MMC_SDHC1_BASE_ADDR},
51 {MMC_SDHC2_BASE_ADDR},
57 /* dram_init must store complete ramsize in gd->ram_size */
58 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
63 u32 get_board_rev(void)
65 u32 rev = get_cpu_rev();
66 if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
67 rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
71 static void setup_iomux_uart(void)
73 unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
74 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
76 mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
77 mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
78 mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
79 mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
80 mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
81 mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
82 mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
83 mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
86 static void setup_iomux_fec(void)
89 mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
90 mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
93 mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
94 mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
97 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
98 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
101 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
102 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
105 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
106 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
109 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
110 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
113 mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
114 mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
117 mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
118 mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
121 mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
122 mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
125 mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
126 mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
129 mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
130 mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
133 mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
134 mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
137 mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
138 mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
141 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
142 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
145 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
146 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
149 mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
150 mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
153 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
154 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
157 mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
158 mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
161 #ifdef CONFIG_MXC_SPI
162 static void setup_iomux_spi(void)
164 /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
165 mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
166 mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
168 /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
169 mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
170 mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
172 /* de-select SS1 of instance: ecspi1. */
173 mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
174 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
176 /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
177 mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
178 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
180 /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
181 mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
182 mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
184 /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
185 mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
186 mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
190 #ifdef CONFIG_USB_EHCI_MX5
191 #define MX51EVK_USBH1_HUB_RST IOMUX_TO_GPIO(MX51_PIN_GPIO1_7) /* GPIO1_7 */
192 #define MX51EVK_USBH1_STP IOMUX_TO_GPIO(MX51_PIN_USBH1_STP) /* GPIO1_27 */
193 #define MX51EVK_USB_CLK_EN_B IOMUX_TO_GPIO(MX51_PIN_EIM_D18) /* GPIO2_1 */
194 #define MX51EVK_USB_PHY_RESET IOMUX_TO_GPIO(MX51_PIN_EIM_D21) /* GPIO2_5 */
196 #define USBH1_PAD (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | \
197 PAD_CTL_100K_PU | PAD_CTL_PUE_PULL | \
198 PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE)
199 #define GPIO_PAD (PAD_CTL_DRV_HIGH | PAD_CTL_PKE_ENABLE | \
201 #define NO_PAD (1 << 16)
203 static void setup_usb_h1(void)
205 setup_iomux_usb_h1();
207 /* GPIO_1_7 for USBH1 hub reset */
208 mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
209 mxc_iomux_set_pad(MX51_PIN_GPIO1_7, NO_PAD);
212 mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT1);
213 mxc_iomux_set_pad(MX51_PIN_EIM_D17, GPIO_PAD);
215 /* GPIO_2_5 for USB PHY reset */
216 mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT1);
217 mxc_iomux_set_pad(MX51_PIN_EIM_D21, GPIO_PAD);
220 int board_ehci_hcd_init(int port)
222 /* Set USBH1_STP to GPIO and toggle it */
223 mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_GPIO);
224 mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
226 gpio_direction_output(MX51EVK_USBH1_STP, 0);
227 gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
229 gpio_set_value(MX51EVK_USBH1_STP, 1);
231 /* Set back USBH1_STP to be function */
232 mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
233 mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
235 /* De-assert USB PHY RESETB */
236 gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
238 /* Drive USB_CLK_EN_B line low */
239 gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0);
242 gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0);
244 gpio_set_value(MX51EVK_USBH1_HUB_RST, 1);
249 static void power_init(void)
252 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
258 /* Write needed to Power Gate 2 register */
259 pmic_reg_read(p, REG_POWER_MISC, &val);
261 pmic_reg_write(p, REG_POWER_MISC, val);
263 /* Externally powered */
264 pmic_reg_read(p, REG_CHARGE, &val);
265 val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
266 pmic_reg_write(p, REG_CHARGE, val);
268 /* power up the system first */
269 pmic_reg_write(p, REG_POWER_MISC, PWUP);
271 /* Set core voltage to 1.1V */
272 pmic_reg_read(p, REG_SW_0, &val);
273 val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
274 pmic_reg_write(p, REG_SW_0, val);
276 /* Setup VCC (SW2) to 1.25 */
277 pmic_reg_read(p, REG_SW_1, &val);
278 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
279 pmic_reg_write(p, REG_SW_1, val);
281 /* Setup 1V2_DIG1 (SW3) to 1.25 */
282 pmic_reg_read(p, REG_SW_2, &val);
283 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
284 pmic_reg_write(p, REG_SW_2, val);
287 /* Raise the core frequency to 800MHz */
288 writel(0x0, &mxc_ccm->cacrr);
290 /* Set switchers in Auto in NORMAL mode & STANDBY mode */
291 /* Setup the switcher mode for SW1 & SW2*/
292 pmic_reg_read(p, REG_SW_4, &val);
293 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
294 (SWMODE_MASK << SWMODE2_SHIFT)));
295 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
296 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
297 pmic_reg_write(p, REG_SW_4, val);
299 /* Setup the switcher mode for SW3 & SW4 */
300 pmic_reg_read(p, REG_SW_5, &val);
301 val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
302 (SWMODE_MASK << SWMODE4_SHIFT)));
303 val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
304 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
305 pmic_reg_write(p, REG_SW_5, val);
307 /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
308 pmic_reg_read(p, REG_SETTING_0, &val);
309 val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
310 val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
311 pmic_reg_write(p, REG_SETTING_0, val);
313 /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
314 pmic_reg_read(p, REG_SETTING_1, &val);
315 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
316 val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
317 pmic_reg_write(p, REG_SETTING_1, val);
319 /* Configure VGEN3 and VCAM regulators to use external PNP */
320 val = VGEN3CONFIG | VCAMCONFIG;
321 pmic_reg_write(p, REG_MODE_1, val);
324 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
325 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
326 VVIDEOEN | VAUDIOEN | VSDEN;
327 pmic_reg_write(p, REG_MODE_1, val);
329 mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1);
330 gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
334 gpio_set_value(IMX_GPIO_NR(2, 14), 1);
337 #ifdef CONFIG_FSL_ESDHC
338 int board_mmc_getcd(struct mmc *mmc)
340 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
343 mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT1);
344 gpio_direction_input(IMX_GPIO_NR(1, 0));
345 mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
346 gpio_direction_input(IMX_GPIO_NR(1, 6));
348 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
349 ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
351 ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
356 int board_mmc_init(bd_t *bis)
361 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
365 mxc_request_iomux(MX51_PIN_SD1_CMD,
366 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
367 mxc_request_iomux(MX51_PIN_SD1_CLK,
368 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
369 mxc_request_iomux(MX51_PIN_SD1_DATA0,
370 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
371 mxc_request_iomux(MX51_PIN_SD1_DATA1,
372 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
373 mxc_request_iomux(MX51_PIN_SD1_DATA2,
374 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
375 mxc_request_iomux(MX51_PIN_SD1_DATA3,
376 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
377 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
378 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
379 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
381 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
382 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
383 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
384 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
386 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
387 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
388 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
389 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
391 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
392 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
393 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
394 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
396 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
397 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
398 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
399 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
401 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
402 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
403 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
404 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
406 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
407 mxc_request_iomux(MX51_PIN_GPIO1_0,
408 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
409 mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
411 mxc_request_iomux(MX51_PIN_GPIO1_1,
412 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
413 mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
417 mxc_request_iomux(MX51_PIN_SD2_CMD,
418 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
419 mxc_request_iomux(MX51_PIN_SD2_CLK,
420 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
421 mxc_request_iomux(MX51_PIN_SD2_DATA0,
423 mxc_request_iomux(MX51_PIN_SD2_DATA1,
425 mxc_request_iomux(MX51_PIN_SD2_DATA2,
427 mxc_request_iomux(MX51_PIN_SD2_DATA3,
429 mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
430 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
432 mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
433 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
435 mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
436 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
438 mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
439 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
441 mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
442 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
444 mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
445 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
447 mxc_request_iomux(MX51_PIN_SD2_CMD,
448 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
449 mxc_request_iomux(MX51_PIN_GPIO1_6,
450 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
451 mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
453 mxc_request_iomux(MX51_PIN_GPIO1_5,
454 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
455 mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
459 printf("Warning: you configured more ESDHC controller"
460 "(%d) as supported by the board(2)\n",
461 CONFIG_SYS_FSL_ESDHC_NUM);
464 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
470 static struct fb_videomode claa_wvga = {
471 .name = "CLAA07LC0ACW",
483 .vmode = FB_VMODE_NONINTERLACED
489 mxc_request_iomux(MX51_PIN_DI_GP4, IOMUX_CONFIG_ALT4);
491 /* Pad settings for MX51_PIN_DI2_DISP_CLK */
492 mxc_iomux_set_pad(MX51_PIN_DI2_DISP_CLK, PAD_CTL_HYS_NONE |
493 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
494 PAD_CTL_DRV_MAX | PAD_CTL_SRE_SLOW);
496 /* Turn on 3.3V voltage for LCD */
497 mxc_request_iomux(MX51_PIN_CSI2_D12, IOMUX_CONFIG_ALT3);
498 gpio_direction_output(MX51EVK_LCD_3V3, 1);
500 /* Turn on 5V voltage for LCD */
501 mxc_request_iomux(MX51_PIN_CSI2_D13, IOMUX_CONFIG_ALT3);
502 gpio_direction_output(MX51EVK_LCD_5V, 1);
504 /* Turn on GPIO backlight */
505 mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
506 mxc_iomux_set_input(MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
508 gpio_direction_output(MX51EVK_LCD_BACKLIGHT, 1);
511 void lcd_enable(void)
513 int ret = ipuv3_fb_init(&claa_wvga, 1, IPU_PIX_FMT_RGB565);
515 printf("LCD cannot be configured: %d\n", ret);
518 int board_early_init_f(void)
522 #ifdef CONFIG_USB_EHCI_MX5
532 /* address of boot parameters */
533 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
540 #ifdef CONFIG_BOARD_LATE_INIT
541 int board_late_init(void)
543 #ifdef CONFIG_MXC_SPI
553 * Do not overwrite the console
554 * Use always serial for U-Boot console
556 int overwrite_console(void)
563 puts("Board: MX51EVK\n");