2 * (C) Copyright 2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/mx5x_pins.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/arch/crm_regs.h>
29 #include <asm/arch/iomux.h>
30 #include <asm/errno.h>
33 #include <fsl_esdhc.h>
36 #define ETHERNET_INT (1 * 32 + 31) /* GPIO2_31 */
38 DECLARE_GLOBAL_DATA_PTR;
40 u32 get_board_rev(void)
49 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
50 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
52 gd->ram_size = size1 + size2;
56 void dram_init_banksize(void)
58 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
59 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
61 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
62 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
65 static void setup_iomux_uart(void)
68 mxc_request_iomux(MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3);
69 mxc_iomux_set_pad(MX53_PIN_ATA_DMACK,
70 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
71 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
72 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
73 PAD_CTL_ODE_OPENDRAIN_ENABLE);
74 mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
77 mxc_request_iomux(MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3);
78 mxc_iomux_set_pad(MX53_PIN_ATA_DIOW,
79 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
80 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
81 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
82 PAD_CTL_ODE_OPENDRAIN_ENABLE);
85 #ifdef CONFIG_FSL_ESDHC
86 struct fsl_esdhc_cfg esdhc_cfg[2] = {
87 {MMC_SDHC1_BASE_ADDR, 1 },
88 {MMC_SDHC2_BASE_ADDR, 1 },
91 int board_mmc_getcd(u8 *cd, struct mmc *mmc)
93 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
95 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
96 *cd = gpio_get_value(1); /*GPIO1_1*/
98 *cd = gpio_get_value(4); /*GPIO1_4*/
103 int board_mmc_init(bd_t *bis)
108 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
111 mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
112 mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
113 mxc_request_iomux(MX53_PIN_SD1_DATA0,
115 mxc_request_iomux(MX53_PIN_SD1_DATA1,
117 mxc_request_iomux(MX53_PIN_SD1_DATA2,
119 mxc_request_iomux(MX53_PIN_SD1_DATA3,
122 mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4);
123 mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4);
124 mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4);
125 mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4);
126 mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4);
127 mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4);
130 mxc_request_iomux(MX53_PIN_SD2_CMD,
131 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
132 mxc_request_iomux(MX53_PIN_SD2_CLK,
133 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
134 mxc_request_iomux(MX53_PIN_SD2_DATA0,
136 mxc_request_iomux(MX53_PIN_SD2_DATA1,
138 mxc_request_iomux(MX53_PIN_SD2_DATA2,
140 mxc_request_iomux(MX53_PIN_SD2_DATA3,
142 mxc_request_iomux(MX53_PIN_ATA_DATA12,
144 mxc_request_iomux(MX53_PIN_ATA_DATA13,
146 mxc_request_iomux(MX53_PIN_ATA_DATA14,
148 mxc_request_iomux(MX53_PIN_ATA_DATA15,
151 mxc_iomux_set_pad(MX53_PIN_SD2_CMD, 0x1E4);
152 mxc_iomux_set_pad(MX53_PIN_SD2_CLK, 0xD4);
153 mxc_iomux_set_pad(MX53_PIN_SD2_DATA0, 0x1D4);
154 mxc_iomux_set_pad(MX53_PIN_SD2_DATA1, 0x1D4);
155 mxc_iomux_set_pad(MX53_PIN_SD2_DATA2, 0x1D4);
156 mxc_iomux_set_pad(MX53_PIN_SD2_DATA3, 0x1D4);
157 mxc_iomux_set_pad(MX53_PIN_ATA_DATA12, 0x1D4);
158 mxc_iomux_set_pad(MX53_PIN_ATA_DATA13, 0x1D4);
159 mxc_iomux_set_pad(MX53_PIN_ATA_DATA14, 0x1D4);
160 mxc_iomux_set_pad(MX53_PIN_ATA_DATA15, 0x1D4);
163 printf("Warning: you configured more ESDHC controller"
164 "(%d) as supported by the board(2)\n",
165 CONFIG_SYS_FSL_ESDHC_NUM);
168 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
175 static void weim_smc911x_iomux(void)
177 /* ETHERNET_INT as GPIO2_31 */
178 mxc_request_iomux(MX53_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
179 gpio_direction_input(ETHERNET_INT);
182 mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT0);
183 mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0xA4);
185 mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT0);
186 mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0xA4);
188 mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT0);
189 mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0xA4);
191 mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT0);
192 mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0xA4);
194 mxc_request_iomux(MX53_PIN_EIM_D20, IOMUX_CONFIG_ALT0);
195 mxc_iomux_set_pad(MX53_PIN_EIM_D20, 0xA4);
197 mxc_request_iomux(MX53_PIN_EIM_D21, IOMUX_CONFIG_ALT0);
198 mxc_iomux_set_pad(MX53_PIN_EIM_D21, 0xA4);
200 mxc_request_iomux(MX53_PIN_EIM_D22, IOMUX_CONFIG_ALT0);
201 mxc_iomux_set_pad(MX53_PIN_EIM_D22, 0xA4);
203 mxc_request_iomux(MX53_PIN_EIM_D23, IOMUX_CONFIG_ALT0);
204 mxc_iomux_set_pad(MX53_PIN_EIM_D23, 0xA4);
206 mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT0);
207 mxc_iomux_set_pad(MX53_PIN_EIM_D24, 0xA4);
209 mxc_request_iomux(MX53_PIN_EIM_D25, IOMUX_CONFIG_ALT0);
210 mxc_iomux_set_pad(MX53_PIN_EIM_D25, 0xA4);
212 mxc_request_iomux(MX53_PIN_EIM_D26, IOMUX_CONFIG_ALT0);
213 mxc_iomux_set_pad(MX53_PIN_EIM_D26, 0xA4);
215 mxc_request_iomux(MX53_PIN_EIM_D27, IOMUX_CONFIG_ALT0);
216 mxc_iomux_set_pad(MX53_PIN_EIM_D27, 0xA4);
218 mxc_request_iomux(MX53_PIN_EIM_D28, IOMUX_CONFIG_ALT0);
219 mxc_iomux_set_pad(MX53_PIN_EIM_D28, 0xA4);
221 mxc_request_iomux(MX53_PIN_EIM_D29, IOMUX_CONFIG_ALT0);
222 mxc_iomux_set_pad(MX53_PIN_EIM_D29, 0xA4);
224 mxc_request_iomux(MX53_PIN_EIM_D30, IOMUX_CONFIG_ALT0);
225 mxc_iomux_set_pad(MX53_PIN_EIM_D30, 0xA4);
227 mxc_request_iomux(MX53_PIN_EIM_D31, IOMUX_CONFIG_ALT0);
228 mxc_iomux_set_pad(MX53_PIN_EIM_D31, 0xA4);
231 mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0);
232 mxc_iomux_set_pad(MX53_PIN_EIM_DA0, 0xA4);
234 mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0);
235 mxc_iomux_set_pad(MX53_PIN_EIM_DA1, 0xA4);
237 mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0);
238 mxc_iomux_set_pad(MX53_PIN_EIM_DA2, 0xA4);
240 mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0);
241 mxc_iomux_set_pad(MX53_PIN_EIM_DA3, 0xA4);
243 mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0);
244 mxc_iomux_set_pad(MX53_PIN_EIM_DA4, 0xA4);
246 mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0);
247 mxc_iomux_set_pad(MX53_PIN_EIM_DA5, 0xA4);
249 mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0);
250 mxc_iomux_set_pad(MX53_PIN_EIM_DA6, 0xA4);
252 /* other EIM signals for ethernet */
253 mxc_request_iomux(MX53_PIN_EIM_OE, IOMUX_CONFIG_ALT0);
254 mxc_request_iomux(MX53_PIN_EIM_RW, IOMUX_CONFIG_ALT0);
255 mxc_request_iomux(MX53_PIN_EIM_CS1, IOMUX_CONFIG_ALT0);
258 static void weim_cs1_settings(void)
260 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
262 writel(MX53ARD_CS1GCR1, &weim_regs->cs1gcr1);
263 writel(0x0, &weim_regs->cs1gcr2);
264 writel(MX53ARD_CS1RCR1, &weim_regs->cs1rcr1);
265 writel(MX53ARD_CS1RCR2, &weim_regs->cs1rcr2);
266 writel(MX53ARD_CS1WCR1, &weim_regs->cs1wcr1);
267 writel(0x0, &weim_regs->cs1wcr2);
268 writel(0x0, &weim_regs->wcr);
270 set_chipselect_size(CS0_64M_CS1_64M);
273 int board_early_init_f(void)
281 gd->bd->bi_arch_number = MACH_TYPE_MX53_ARD;
282 /* address of boot parameters */
283 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
288 int board_eth_init(bd_t *bis)
292 weim_smc911x_iomux();
295 #ifdef CONFIG_SMC911X
296 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
303 puts("Board: MX53ARD\n");