2 * (C) Copyright 2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/mx5x_pins.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/arch/crm_regs.h>
29 #include <asm/arch/clock.h>
30 #include <asm/arch/iomux.h>
31 #include <asm/errno.h>
34 #include <fsl_esdhc.h>
37 #define ETHERNET_INT IMX_GPIO_NR(2, 31)
39 DECLARE_GLOBAL_DATA_PTR;
45 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
46 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
48 gd->ram_size = size1 + size2;
52 void dram_init_banksize(void)
54 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
55 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
57 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
58 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
61 #ifdef CONFIG_NAND_MXC
62 static void setup_iomux_nand(void)
65 #define M4IF_GENP_WEIM_MM_MASK 0x00000001
66 #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000
68 reg = __raw_readl(M4IF_BASE_ADDR + 0xc);
69 reg &= ~M4IF_GENP_WEIM_MM_MASK;
70 __raw_writel(reg, M4IF_BASE_ADDR + 0xc);
71 for (i = 0x4; i < 0x94; i += 0x18) {
72 reg = __raw_readl(WEIM_BASE_ADDR + i);
73 reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK;
74 __raw_writel(reg, WEIM_BASE_ADDR + i);
77 mxc_request_iomux(MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
78 mxc_iomux_set_pad(MX53_PIN_NANDF_CS0, PAD_CTL_DRV_HIGH);
79 mxc_request_iomux(MX53_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0);
80 mxc_iomux_set_pad(MX53_PIN_NANDF_CS1, PAD_CTL_DRV_HIGH);
81 mxc_request_iomux(MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0);
82 mxc_iomux_set_pad(MX53_PIN_NANDF_RB0, PAD_CTL_PKE_ENABLE |
83 PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
84 mxc_request_iomux(MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0);
85 mxc_iomux_set_pad(MX53_PIN_NANDF_CLE, PAD_CTL_DRV_HIGH);
86 mxc_request_iomux(MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0);
87 mxc_iomux_set_pad(MX53_PIN_NANDF_ALE, PAD_CTL_DRV_HIGH);
88 mxc_request_iomux(MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0);
89 mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B, PAD_CTL_PKE_ENABLE |
90 PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
91 mxc_request_iomux(MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0);
92 mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B, PAD_CTL_DRV_HIGH);
93 mxc_request_iomux(MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0);
94 mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B, PAD_CTL_DRV_HIGH);
95 mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0);
96 mxc_iomux_set_pad(MX53_PIN_EIM_DA0, PAD_CTL_PKE_ENABLE |
97 PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
98 mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0);
99 mxc_iomux_set_pad(MX53_PIN_EIM_DA1, PAD_CTL_PKE_ENABLE |
100 PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
101 mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0);
102 mxc_iomux_set_pad(MX53_PIN_EIM_DA2, PAD_CTL_PKE_ENABLE |
103 PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
104 mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0);
105 mxc_iomux_set_pad(MX53_PIN_EIM_DA3, PAD_CTL_PKE_ENABLE |
106 PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
107 mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0);
108 mxc_iomux_set_pad(MX53_PIN_EIM_DA4, PAD_CTL_PKE_ENABLE |
109 PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
110 mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0);
111 mxc_iomux_set_pad(MX53_PIN_EIM_DA5, PAD_CTL_PKE_ENABLE |
112 PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
113 mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0);
114 mxc_iomux_set_pad(MX53_PIN_EIM_DA6, PAD_CTL_PKE_ENABLE |
115 PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
116 mxc_request_iomux(MX53_PIN_EIM_DA7, IOMUX_CONFIG_ALT0);
117 mxc_iomux_set_pad(MX53_PIN_EIM_DA7, PAD_CTL_PKE_ENABLE |
118 PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
121 static void setup_iomux_nand(void)
126 static void setup_iomux_uart(void)
129 mxc_request_iomux(MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3);
130 mxc_iomux_set_pad(MX53_PIN_ATA_DMACK,
131 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
132 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
133 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
134 PAD_CTL_ODE_OPENDRAIN_ENABLE);
135 mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
138 mxc_request_iomux(MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3);
139 mxc_iomux_set_pad(MX53_PIN_ATA_DIOW,
140 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
141 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
142 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
143 PAD_CTL_ODE_OPENDRAIN_ENABLE);
146 #ifdef CONFIG_FSL_ESDHC
147 struct fsl_esdhc_cfg esdhc_cfg[2] = {
148 {MMC_SDHC1_BASE_ADDR},
149 {MMC_SDHC2_BASE_ADDR},
152 int board_mmc_getcd(struct mmc *mmc)
154 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
157 mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
158 gpio_direction_input(IMX_GPIO_NR(1, 1));
159 mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1);
160 gpio_direction_input(IMX_GPIO_NR(1, 4));
162 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
163 ret = !gpio_get_value(IMX_GPIO_NR(1, 1));
165 ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
170 int board_mmc_init(bd_t *bis)
175 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
176 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
178 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
181 mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
182 mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
183 mxc_request_iomux(MX53_PIN_SD1_DATA0,
185 mxc_request_iomux(MX53_PIN_SD1_DATA1,
187 mxc_request_iomux(MX53_PIN_SD1_DATA2,
189 mxc_request_iomux(MX53_PIN_SD1_DATA3,
192 mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4);
193 mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4);
194 mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4);
195 mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4);
196 mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4);
197 mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4);
200 mxc_request_iomux(MX53_PIN_SD2_CMD,
201 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
202 mxc_request_iomux(MX53_PIN_SD2_CLK,
203 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
204 mxc_request_iomux(MX53_PIN_SD2_DATA0,
206 mxc_request_iomux(MX53_PIN_SD2_DATA1,
208 mxc_request_iomux(MX53_PIN_SD2_DATA2,
210 mxc_request_iomux(MX53_PIN_SD2_DATA3,
212 mxc_request_iomux(MX53_PIN_ATA_DATA12,
214 mxc_request_iomux(MX53_PIN_ATA_DATA13,
216 mxc_request_iomux(MX53_PIN_ATA_DATA14,
218 mxc_request_iomux(MX53_PIN_ATA_DATA15,
221 mxc_iomux_set_pad(MX53_PIN_SD2_CMD, 0x1E4);
222 mxc_iomux_set_pad(MX53_PIN_SD2_CLK, 0xD4);
223 mxc_iomux_set_pad(MX53_PIN_SD2_DATA0, 0x1D4);
224 mxc_iomux_set_pad(MX53_PIN_SD2_DATA1, 0x1D4);
225 mxc_iomux_set_pad(MX53_PIN_SD2_DATA2, 0x1D4);
226 mxc_iomux_set_pad(MX53_PIN_SD2_DATA3, 0x1D4);
227 mxc_iomux_set_pad(MX53_PIN_ATA_DATA12, 0x1D4);
228 mxc_iomux_set_pad(MX53_PIN_ATA_DATA13, 0x1D4);
229 mxc_iomux_set_pad(MX53_PIN_ATA_DATA14, 0x1D4);
230 mxc_iomux_set_pad(MX53_PIN_ATA_DATA15, 0x1D4);
233 printf("Warning: you configured more ESDHC controller"
234 "(%d) as supported by the board(2)\n",
235 CONFIG_SYS_FSL_ESDHC_NUM);
238 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
245 static void weim_smc911x_iomux(void)
247 /* ETHERNET_INT as GPIO2_31 */
248 mxc_request_iomux(MX53_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
249 gpio_direction_input(ETHERNET_INT);
252 mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT0);
253 mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0xA4);
255 mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT0);
256 mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0xA4);
258 mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT0);
259 mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0xA4);
261 mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT0);
262 mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0xA4);
264 mxc_request_iomux(MX53_PIN_EIM_D20, IOMUX_CONFIG_ALT0);
265 mxc_iomux_set_pad(MX53_PIN_EIM_D20, 0xA4);
267 mxc_request_iomux(MX53_PIN_EIM_D21, IOMUX_CONFIG_ALT0);
268 mxc_iomux_set_pad(MX53_PIN_EIM_D21, 0xA4);
270 mxc_request_iomux(MX53_PIN_EIM_D22, IOMUX_CONFIG_ALT0);
271 mxc_iomux_set_pad(MX53_PIN_EIM_D22, 0xA4);
273 mxc_request_iomux(MX53_PIN_EIM_D23, IOMUX_CONFIG_ALT0);
274 mxc_iomux_set_pad(MX53_PIN_EIM_D23, 0xA4);
276 mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT0);
277 mxc_iomux_set_pad(MX53_PIN_EIM_D24, 0xA4);
279 mxc_request_iomux(MX53_PIN_EIM_D25, IOMUX_CONFIG_ALT0);
280 mxc_iomux_set_pad(MX53_PIN_EIM_D25, 0xA4);
282 mxc_request_iomux(MX53_PIN_EIM_D26, IOMUX_CONFIG_ALT0);
283 mxc_iomux_set_pad(MX53_PIN_EIM_D26, 0xA4);
285 mxc_request_iomux(MX53_PIN_EIM_D27, IOMUX_CONFIG_ALT0);
286 mxc_iomux_set_pad(MX53_PIN_EIM_D27, 0xA4);
288 mxc_request_iomux(MX53_PIN_EIM_D28, IOMUX_CONFIG_ALT0);
289 mxc_iomux_set_pad(MX53_PIN_EIM_D28, 0xA4);
291 mxc_request_iomux(MX53_PIN_EIM_D29, IOMUX_CONFIG_ALT0);
292 mxc_iomux_set_pad(MX53_PIN_EIM_D29, 0xA4);
294 mxc_request_iomux(MX53_PIN_EIM_D30, IOMUX_CONFIG_ALT0);
295 mxc_iomux_set_pad(MX53_PIN_EIM_D30, 0xA4);
297 mxc_request_iomux(MX53_PIN_EIM_D31, IOMUX_CONFIG_ALT0);
298 mxc_iomux_set_pad(MX53_PIN_EIM_D31, 0xA4);
301 mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0);
302 mxc_iomux_set_pad(MX53_PIN_EIM_DA0, 0xA4);
304 mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0);
305 mxc_iomux_set_pad(MX53_PIN_EIM_DA1, 0xA4);
307 mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0);
308 mxc_iomux_set_pad(MX53_PIN_EIM_DA2, 0xA4);
310 mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0);
311 mxc_iomux_set_pad(MX53_PIN_EIM_DA3, 0xA4);
313 mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0);
314 mxc_iomux_set_pad(MX53_PIN_EIM_DA4, 0xA4);
316 mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0);
317 mxc_iomux_set_pad(MX53_PIN_EIM_DA5, 0xA4);
319 mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0);
320 mxc_iomux_set_pad(MX53_PIN_EIM_DA6, 0xA4);
322 /* other EIM signals for ethernet */
323 mxc_request_iomux(MX53_PIN_EIM_OE, IOMUX_CONFIG_ALT0);
324 mxc_request_iomux(MX53_PIN_EIM_RW, IOMUX_CONFIG_ALT0);
325 mxc_request_iomux(MX53_PIN_EIM_CS1, IOMUX_CONFIG_ALT0);
328 static void weim_cs1_settings(void)
330 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
332 writel(MX53ARD_CS1GCR1, &weim_regs->cs1gcr1);
333 writel(0x0, &weim_regs->cs1gcr2);
334 writel(MX53ARD_CS1RCR1, &weim_regs->cs1rcr1);
335 writel(MX53ARD_CS1RCR2, &weim_regs->cs1rcr2);
336 writel(MX53ARD_CS1WCR1, &weim_regs->cs1wcr1);
337 writel(0x0, &weim_regs->cs1wcr2);
338 writel(0x0, &weim_regs->wcr);
340 set_chipselect_size(CS0_64M_CS1_64M);
343 int board_early_init_f(void)
352 /* address of boot parameters */
353 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
358 int board_eth_init(bd_t *bis)
362 weim_smc911x_iomux();
365 #ifdef CONFIG_SMC911X
366 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
373 puts("Board: MX53ARD\n");