git.sur5r.net Git - u-boot/blob - board/freescale/mx53ard/mx53ard.c

   1 /*
   2  * (C) Copyright 2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/mx5x_pins.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <asm/arch/iomux.h>
  30 #include <asm/errno.h>
  31 #include <netdev.h>
  32 #include <mmc.h>
  33 #include <fsl_esdhc.h>
  34 #include <asm/gpio.h>
  35
  36 #define ETHERNET_INT            (1 * 32 + 31)  /* GPIO2_31 */
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 int dram_init(void)
  41 {
  42         u32 size1, size2;
  43
  44         size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  45         size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  46
  47         gd->ram_size = size1 + size2;
  48
  49         return 0;
  50 }
  51 void dram_init_banksize(void)
  52 {
  53         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  54         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  55
  56         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  57         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  58 }
  59
  60 static void setup_iomux_uart(void)
  61 {
  62         /* UART1 RXD */
  63         mxc_request_iomux(MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3);
  64         mxc_iomux_set_pad(MX53_PIN_ATA_DMACK,
  65                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  66                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  67                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  68                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  69         mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
  70
  71         /* UART1 TXD */
  72         mxc_request_iomux(MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3);
  73         mxc_iomux_set_pad(MX53_PIN_ATA_DIOW,
  74                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  75                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  76                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  77                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  78 }
  79
  80 #ifdef CONFIG_FSL_ESDHC
  81 struct fsl_esdhc_cfg esdhc_cfg[2] = {
  82         {MMC_SDHC1_BASE_ADDR, 1 },
  83         {MMC_SDHC2_BASE_ADDR, 1 },
  84 };
  85
  86 int board_mmc_getcd(struct mmc *mmc)
  87 {
  88         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  89         int ret;
  90
  91         mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
  92         mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1);
  93
  94         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
  95                 ret = !gpio_get_value(1); /* GPIO1_1 */
  96         else
  97                 ret = !gpio_get_value(4); /* GPIO1_4 */
  98
  99         return ret;
 100 }
 101
 102 int board_mmc_init(bd_t *bis)
 103 {
 104         u32 index;
 105         s32 status = 0;
 106
 107         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 108                 switch (index) {
 109                 case 0:
 110                         mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
 111                         mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
 112                         mxc_request_iomux(MX53_PIN_SD1_DATA0,
 113                                                 IOMUX_CONFIG_ALT0);
 114                         mxc_request_iomux(MX53_PIN_SD1_DATA1,
 115                                                 IOMUX_CONFIG_ALT0);
 116                         mxc_request_iomux(MX53_PIN_SD1_DATA2,
 117                                                 IOMUX_CONFIG_ALT0);
 118                         mxc_request_iomux(MX53_PIN_SD1_DATA3,
 119                                                 IOMUX_CONFIG_ALT0);
 120
 121                         mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4);
 122                         mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4);
 123                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4);
 124                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4);
 125                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4);
 126                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4);
 127                         break;
 128                 case 1:
 129                         mxc_request_iomux(MX53_PIN_SD2_CMD,
 130                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 131                         mxc_request_iomux(MX53_PIN_SD2_CLK,
 132                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 133                         mxc_request_iomux(MX53_PIN_SD2_DATA0,
 134                                                 IOMUX_CONFIG_ALT0);
 135                         mxc_request_iomux(MX53_PIN_SD2_DATA1,
 136                                                 IOMUX_CONFIG_ALT0);
 137                         mxc_request_iomux(MX53_PIN_SD2_DATA2,
 138                                                 IOMUX_CONFIG_ALT0);
 139                         mxc_request_iomux(MX53_PIN_SD2_DATA3,
 140                                                 IOMUX_CONFIG_ALT0);
 141                         mxc_request_iomux(MX53_PIN_ATA_DATA12,
 142                                                 IOMUX_CONFIG_ALT2);
 143                         mxc_request_iomux(MX53_PIN_ATA_DATA13,
 144                                                 IOMUX_CONFIG_ALT2);
 145                         mxc_request_iomux(MX53_PIN_ATA_DATA14,
 146                                                 IOMUX_CONFIG_ALT2);
 147                         mxc_request_iomux(MX53_PIN_ATA_DATA15,
 148                                                 IOMUX_CONFIG_ALT2);
 149
 150                         mxc_iomux_set_pad(MX53_PIN_SD2_CMD, 0x1E4);
 151                         mxc_iomux_set_pad(MX53_PIN_SD2_CLK, 0xD4);
 152                         mxc_iomux_set_pad(MX53_PIN_SD2_DATA0, 0x1D4);
 153                         mxc_iomux_set_pad(MX53_PIN_SD2_DATA1, 0x1D4);
 154                         mxc_iomux_set_pad(MX53_PIN_SD2_DATA2, 0x1D4);
 155                         mxc_iomux_set_pad(MX53_PIN_SD2_DATA3, 0x1D4);
 156                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA12, 0x1D4);
 157                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA13, 0x1D4);
 158                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA14, 0x1D4);
 159                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA15, 0x1D4);
 160                         break;
 161                 default:
 162                         printf("Warning: you configured more ESDHC controller"
 163                                 "(%d) as supported by the board(2)\n",
 164                                 CONFIG_SYS_FSL_ESDHC_NUM);
 165                         return status;
 166                 }
 167                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 168         }
 169
 170         return status;
 171 }
 172 #endif
 173
 174 static void weim_smc911x_iomux(void)
 175 {
 176         /* ETHERNET_INT as GPIO2_31 */
 177         mxc_request_iomux(MX53_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
 178         gpio_direction_input(ETHERNET_INT);
 179
 180         /* Data bus */
 181         mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT0);
 182         mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0xA4);
 183
 184         mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT0);
 185         mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0xA4);
 186
 187         mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT0);
 188         mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0xA4);
 189
 190         mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT0);
 191         mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0xA4);
 192
 193         mxc_request_iomux(MX53_PIN_EIM_D20, IOMUX_CONFIG_ALT0);
 194         mxc_iomux_set_pad(MX53_PIN_EIM_D20, 0xA4);
 195
 196         mxc_request_iomux(MX53_PIN_EIM_D21, IOMUX_CONFIG_ALT0);
 197         mxc_iomux_set_pad(MX53_PIN_EIM_D21, 0xA4);
 198
 199         mxc_request_iomux(MX53_PIN_EIM_D22, IOMUX_CONFIG_ALT0);
 200         mxc_iomux_set_pad(MX53_PIN_EIM_D22, 0xA4);
 201
 202         mxc_request_iomux(MX53_PIN_EIM_D23, IOMUX_CONFIG_ALT0);
 203         mxc_iomux_set_pad(MX53_PIN_EIM_D23, 0xA4);
 204
 205         mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT0);
 206         mxc_iomux_set_pad(MX53_PIN_EIM_D24, 0xA4);
 207
 208         mxc_request_iomux(MX53_PIN_EIM_D25, IOMUX_CONFIG_ALT0);
 209         mxc_iomux_set_pad(MX53_PIN_EIM_D25, 0xA4);
 210
 211         mxc_request_iomux(MX53_PIN_EIM_D26, IOMUX_CONFIG_ALT0);
 212         mxc_iomux_set_pad(MX53_PIN_EIM_D26, 0xA4);
 213
 214         mxc_request_iomux(MX53_PIN_EIM_D27, IOMUX_CONFIG_ALT0);
 215         mxc_iomux_set_pad(MX53_PIN_EIM_D27, 0xA4);
 216
 217         mxc_request_iomux(MX53_PIN_EIM_D28, IOMUX_CONFIG_ALT0);
 218         mxc_iomux_set_pad(MX53_PIN_EIM_D28, 0xA4);
 219
 220         mxc_request_iomux(MX53_PIN_EIM_D29, IOMUX_CONFIG_ALT0);
 221         mxc_iomux_set_pad(MX53_PIN_EIM_D29, 0xA4);
 222
 223         mxc_request_iomux(MX53_PIN_EIM_D30, IOMUX_CONFIG_ALT0);
 224         mxc_iomux_set_pad(MX53_PIN_EIM_D30, 0xA4);
 225
 226         mxc_request_iomux(MX53_PIN_EIM_D31, IOMUX_CONFIG_ALT0);
 227         mxc_iomux_set_pad(MX53_PIN_EIM_D31, 0xA4);
 228
 229         /* Address lines */
 230         mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0);
 231         mxc_iomux_set_pad(MX53_PIN_EIM_DA0, 0xA4);
 232
 233         mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0);
 234         mxc_iomux_set_pad(MX53_PIN_EIM_DA1, 0xA4);
 235
 236         mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0);
 237         mxc_iomux_set_pad(MX53_PIN_EIM_DA2, 0xA4);
 238
 239         mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0);
 240         mxc_iomux_set_pad(MX53_PIN_EIM_DA3, 0xA4);
 241
 242         mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0);
 243         mxc_iomux_set_pad(MX53_PIN_EIM_DA4, 0xA4);
 244
 245         mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0);
 246         mxc_iomux_set_pad(MX53_PIN_EIM_DA5, 0xA4);
 247
 248         mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0);
 249         mxc_iomux_set_pad(MX53_PIN_EIM_DA6, 0xA4);
 250
 251         /* other EIM signals for ethernet */
 252         mxc_request_iomux(MX53_PIN_EIM_OE, IOMUX_CONFIG_ALT0);
 253         mxc_request_iomux(MX53_PIN_EIM_RW, IOMUX_CONFIG_ALT0);
 254         mxc_request_iomux(MX53_PIN_EIM_CS1, IOMUX_CONFIG_ALT0);
 255 }
 256
 257 static void weim_cs1_settings(void)
 258 {
 259         struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
 260
 261         writel(MX53ARD_CS1GCR1, &weim_regs->cs1gcr1);
 262         writel(0x0, &weim_regs->cs1gcr2);
 263         writel(MX53ARD_CS1RCR1, &weim_regs->cs1rcr1);
 264         writel(MX53ARD_CS1RCR2, &weim_regs->cs1rcr2);
 265         writel(MX53ARD_CS1WCR1, &weim_regs->cs1wcr1);
 266         writel(0x0, &weim_regs->cs1wcr2);
 267         writel(0x0, &weim_regs->wcr);
 268
 269         set_chipselect_size(CS0_64M_CS1_64M);
 270 }
 271
 272 int board_early_init_f(void)
 273 {
 274         setup_iomux_uart();
 275         return 0;
 276 }
 277
 278 int board_init(void)
 279 {
 280         /* address of boot parameters */
 281         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 282
 283         return 0;
 284 }
 285
 286 int board_eth_init(bd_t *bis)
 287 {
 288         int rc = 0;
 289
 290         weim_smc911x_iomux();
 291         weim_cs1_settings();
 292
 293 #ifdef CONFIG_SMC911X
 294         rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 295 #endif
 296         return rc;
 297 }
 298
 299 int checkboard(void)
 300 {
 301         puts("Board: MX53ARD\n");
 302
 303         return 0;
 304 }