git.sur5r.net Git - u-boot/blob - board/freescale/mx53evk/mx53evk.c

   1 /*
   2  * (C) Copyright 2010 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/mx5x_pins.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <asm/arch/clock.h>
  30 #include <asm/arch/iomux.h>
  31 #include <asm/errno.h>
  32 #include <asm/imx-common/boot_mode.h>
  33 #include <netdev.h>
  34 #include <i2c.h>
  35 #include <mmc.h>
  36 #include <fsl_esdhc.h>
  37 #include <power/pmic.h>
  38 #include <fsl_pmic.h>
  39 #include <asm/gpio.h>
  40 #include <mc13892.h>
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 int dram_init(void)
  45 {
  46         /* dram_init must store complete ramsize in gd->ram_size */
  47         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  48                                 PHYS_SDRAM_1_SIZE);
  49         return 0;
  50 }
  51
  52 static void setup_iomux_uart(void)
  53 {
  54         /* UART1 RXD */
  55         mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
  56         mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
  57                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  58                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  59                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  60                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  61         mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
  62
  63         /* UART1 TXD */
  64         mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
  65         mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
  66                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  67                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  68                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  69                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  70 }
  71
  72 static void setup_i2c(unsigned int port_number)
  73 {
  74         switch (port_number) {
  75         case 0:
  76                 /* i2c1 SDA */
  77                 mxc_request_iomux(MX53_PIN_CSI0_D8,
  78                                 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
  79                 mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
  80                                 INPUT_CTL_PATH0);
  81                 mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
  82                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
  83                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
  84                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  85                 /* i2c1 SCL */
  86                 mxc_request_iomux(MX53_PIN_CSI0_D9,
  87                                 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
  88                 mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
  89                                 INPUT_CTL_PATH0);
  90                 mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
  91                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
  92                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
  93                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  94                 break;
  95         case 1:
  96                 /* i2c2 SDA */
  97                 mxc_request_iomux(MX53_PIN_KEY_ROW3,
  98                                 IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
  99                 mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
 100                                 INPUT_CTL_PATH0);
 101                 mxc_iomux_set_pad(MX53_PIN_KEY_ROW3,
 102                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
 103                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
 104                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
 105
 106                 /* i2c2 SCL */
 107                 mxc_request_iomux(MX53_PIN_KEY_COL3,
 108                                 IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
 109                 mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
 110                                 INPUT_CTL_PATH0);
 111                 mxc_iomux_set_pad(MX53_PIN_KEY_COL3,
 112                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
 113                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
 114                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
 115                 break;
 116         default:
 117                 printf("Warning: Wrong I2C port number\n");
 118                 break;
 119         }
 120 }
 121
 122 void power_init(void)
 123 {
 124         unsigned int val;
 125         struct pmic *p;
 126         int ret;
 127
 128         ret = pmic_init(I2C_PMIC);
 129         if (ret)
 130                 return;
 131
 132         p = pmic_get("FSL_PMIC");
 133         if (!p)
 134                 return;
 135
 136         /* Set VDDA to 1.25V */
 137         pmic_reg_read(p, REG_SW_2, &val);
 138         val &= ~SWX_OUT_MASK;
 139         val |= SWX_OUT_1_25;
 140         pmic_reg_write(p, REG_SW_2, val);
 141
 142         /*
 143          * Need increase VCC and VDDA to 1.3V
 144          * according to MX53 IC TO2 datasheet.
 145          */
 146         if (is_soc_rev(CHIP_REV_2_0) == 0) {
 147                 /* Set VCC to 1.3V for TO2 */
 148                 pmic_reg_read(p, REG_SW_1, &val);
 149                 val &= ~SWX_OUT_MASK;
 150                 val |= SWX_OUT_1_30;
 151                 pmic_reg_write(p, REG_SW_1, val);
 152
 153                 /* Set VDDA to 1.3V for TO2 */
 154                 pmic_reg_read(p, REG_SW_2, &val);
 155                 val &= ~SWX_OUT_MASK;
 156                 val |= SWX_OUT_1_30;
 157                 pmic_reg_write(p, REG_SW_2, val);
 158         }
 159 }
 160
 161 static void setup_iomux_fec(void)
 162 {
 163         /*FEC_MDIO*/
 164         mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
 165         mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
 166                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 167                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 168                                 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
 169         mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
 170
 171         /*FEC_MDC*/
 172         mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
 173         mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
 174
 175         /* FEC RXD1 */
 176         mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
 177         mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
 178                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 179
 180         /* FEC RXD0 */
 181         mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
 182         mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
 183                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 184
 185          /* FEC TXD1 */
 186         mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
 187         mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
 188
 189         /* FEC TXD0 */
 190         mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
 191         mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
 192
 193         /* FEC TX_EN */
 194         mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
 195         mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
 196
 197         /* FEC TX_CLK */
 198         mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
 199         mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
 200                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 201
 202         /* FEC RX_ER */
 203         mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
 204         mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
 205                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 206
 207         /* FEC CRS */
 208         mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
 209         mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
 210                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 211 }
 212
 213 #ifdef CONFIG_FSL_ESDHC
 214 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 215         {MMC_SDHC1_BASE_ADDR},
 216         {MMC_SDHC3_BASE_ADDR},
 217 };
 218
 219 int board_mmc_getcd(struct mmc *mmc)
 220 {
 221         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 222         int ret;
 223
 224         mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
 225         gpio_direction_input(IMX_GPIO_NR(3, 11));
 226         mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
 227         gpio_direction_input(IMX_GPIO_NR(3, 13));
 228
 229         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 230                 ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
 231         else
 232                 ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
 233
 234         return ret;
 235 }
 236
 237 int board_mmc_init(bd_t *bis)
 238 {
 239         u32 index;
 240         s32 status = 0;
 241
 242         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 243         esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 244
 245         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 246                 switch (index) {
 247                 case 0:
 248                         mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
 249                         mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
 250                         mxc_request_iomux(MX53_PIN_SD1_DATA0,
 251                                                 IOMUX_CONFIG_ALT0);
 252                         mxc_request_iomux(MX53_PIN_SD1_DATA1,
 253                                                 IOMUX_CONFIG_ALT0);
 254                         mxc_request_iomux(MX53_PIN_SD1_DATA2,
 255                                                 IOMUX_CONFIG_ALT0);
 256                         mxc_request_iomux(MX53_PIN_SD1_DATA3,
 257                                                 IOMUX_CONFIG_ALT0);
 258                         mxc_request_iomux(MX53_PIN_EIM_DA13,
 259                                                 IOMUX_CONFIG_ALT1);
 260
 261                         mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
 262                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 263                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 264                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
 265                         mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
 266                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 267                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 268                                 PAD_CTL_DRV_HIGH);
 269                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
 270                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 271                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 272                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 273                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
 274                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 275                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 276                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 277                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
 278                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 279                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 280                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 281                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
 282                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 283                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 284                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 285                         break;
 286                 case 1:
 287                         mxc_request_iomux(MX53_PIN_ATA_RESET_B,
 288                                                 IOMUX_CONFIG_ALT2);
 289                         mxc_request_iomux(MX53_PIN_ATA_IORDY,
 290                                                 IOMUX_CONFIG_ALT2);
 291                         mxc_request_iomux(MX53_PIN_ATA_DATA8,
 292                                                 IOMUX_CONFIG_ALT4);
 293                         mxc_request_iomux(MX53_PIN_ATA_DATA9,
 294                                                 IOMUX_CONFIG_ALT4);
 295                         mxc_request_iomux(MX53_PIN_ATA_DATA10,
 296                                                 IOMUX_CONFIG_ALT4);
 297                         mxc_request_iomux(MX53_PIN_ATA_DATA11,
 298                                                 IOMUX_CONFIG_ALT4);
 299                         mxc_request_iomux(MX53_PIN_ATA_DATA0,
 300                                                 IOMUX_CONFIG_ALT4);
 301                         mxc_request_iomux(MX53_PIN_ATA_DATA1,
 302                                                 IOMUX_CONFIG_ALT4);
 303                         mxc_request_iomux(MX53_PIN_ATA_DATA2,
 304                                                 IOMUX_CONFIG_ALT4);
 305                         mxc_request_iomux(MX53_PIN_ATA_DATA3,
 306                                                 IOMUX_CONFIG_ALT4);
 307                         mxc_request_iomux(MX53_PIN_EIM_DA11,
 308                                                 IOMUX_CONFIG_ALT1);
 309
 310                         mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
 311                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 312                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 313                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
 314                         mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
 315                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 316                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 317                                 PAD_CTL_DRV_HIGH);
 318                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
 319                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 320                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 321                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 322                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
 323                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 324                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 325                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 326                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
 327                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 328                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 329                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 330                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
 331                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 332                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 333                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 334                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
 335                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 336                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 337                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 338                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
 339                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 340                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 341                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 342                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
 343                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 344                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 345                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 346                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
 347                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 348                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 349                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 350
 351                         break;
 352                 default:
 353                         printf("Warning: you configured more ESDHC controller"
 354                                 "(%d) as supported by the board(2)\n",
 355                                 CONFIG_SYS_FSL_ESDHC_NUM);
 356                         return status;
 357                 }
 358                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 359         }
 360
 361         return status;
 362 }
 363 #endif
 364
 365 int board_early_init_f(void)
 366 {
 367         setup_iomux_uart();
 368         setup_iomux_fec();
 369
 370         return 0;
 371 }
 372
 373 int board_init(void)
 374 {
 375         /* address of boot parameters */
 376         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 377
 378         return 0;
 379 }
 380
 381 #ifdef CONFIG_CMD_BMODE
 382 static const struct boot_mode board_boot_modes[] = {
 383         /* 4 bit bus width */
 384         {"mmc0",        MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
 385         {"mmc1",        MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
 386         {NULL,          0},
 387 };
 388 #endif
 389
 390 int board_late_init(void)
 391 {
 392         setup_i2c(1);
 393         power_init();
 394
 395 #ifdef CONFIG_CMD_BMODE
 396         add_board_boot_modes(board_boot_modes);
 397 #endif
 398         return 0;
 399 }
 400
 401 int checkboard(void)
 402 {
 403         puts("Board: MX53EVK\n");
 404
 405         return 0;
 406 }