2 * (C) Copyright 2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/mx5x_pins.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/arch/crm_regs.h>
29 #include <asm/arch/clock.h>
30 #include <asm/arch/iomux.h>
31 #include <asm/errno.h>
34 #include <fsl_esdhc.h>
37 DECLARE_GLOBAL_DATA_PTR;
43 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
44 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
46 gd->ram_size = size1 + size2;
50 void dram_init_banksize(void)
52 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
53 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
55 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
56 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
59 static void setup_iomux_uart(void)
62 mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
63 mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
64 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
65 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
66 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
67 PAD_CTL_ODE_OPENDRAIN_ENABLE);
68 mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
71 mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
72 mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
73 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
74 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
75 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
76 PAD_CTL_ODE_OPENDRAIN_ENABLE);
79 static void setup_iomux_fec(void)
82 mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
83 mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
84 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
85 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
86 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
87 mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
90 mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
91 mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
94 mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
95 mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
96 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
99 mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
100 mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
101 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
104 mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
105 mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
108 mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
109 mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
112 mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
113 mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
116 mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
117 mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
118 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
121 mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
122 mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
123 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
126 mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
127 mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
128 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
131 #ifdef CONFIG_FSL_ESDHC
132 struct fsl_esdhc_cfg esdhc_cfg[1] = {
133 {MMC_SDHC1_BASE_ADDR},
136 int board_mmc_getcd(struct mmc *mmc)
138 mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
139 gpio_direction_input(IMX_GPIO_NR(3, 13));
140 return !gpio_get_value(IMX_GPIO_NR(3, 13));
143 int board_mmc_init(bd_t *bis)
148 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
150 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
153 mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
154 mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
155 mxc_request_iomux(MX53_PIN_SD1_DATA0,
157 mxc_request_iomux(MX53_PIN_SD1_DATA1,
159 mxc_request_iomux(MX53_PIN_SD1_DATA2,
161 mxc_request_iomux(MX53_PIN_SD1_DATA3,
163 mxc_request_iomux(MX53_PIN_EIM_DA13,
166 mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
167 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
168 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
169 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
170 mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
171 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
172 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
174 mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
175 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
176 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
177 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
178 mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
179 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
180 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
181 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
182 mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
183 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
184 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
185 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
186 mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
187 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
188 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
189 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
193 printf("Warning: you configured more ESDHC controller"
194 "(%d) as supported by the board(1)\n",
195 CONFIG_SYS_FSL_ESDHC_NUM);
198 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
205 int board_early_init_f(void)
215 /* address of boot parameters */
216 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
223 puts("Board: MX53SMD\n");