2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 * Jason Liu <r64343@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
7 * Refer doc/README.imximage for more details about how-to configure
8 * and create imximage boot image
10 * The syntax is taken as close as possible with the kwbimage
17 * Boot Device : one of
18 * spi, sd (the board has no nand neither onenand)
23 * Device Configuration Data (DCD)
25 * Each entry must have the format:
26 * Addr-type Address Value
29 * Addr-type register length (1,2 or 4 bytes)
30 * Address absolute address of the register
31 * value value to be stored in the register
36 #ifdef CONFIG_MX6DL_LPDDR2
39 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
40 DATA 4 0x020E04bc 0x00003028
41 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
42 DATA 4 0x020E04c0 0x00003028
43 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */
44 DATA 4 0x020E04c4 0x00003028
45 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */
46 DATA 4 0x020E04c8 0x00003028
47 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */
48 DATA 4 0x020E04cc 0x00003028
49 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */
50 DATA 4 0x020E04d0 0x00003028
51 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */
52 DATA 4 0x020E04d4 0x00003028
53 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */
54 DATA 4 0x020E04d8 0x00003028
56 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
57 DATA 4 0x020E0470 0x00000038
58 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
59 DATA 4 0x020E0474 0x00000038
60 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */
61 DATA 4 0x020E0478 0x00000038
62 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */
63 DATA 4 0x020E047c 0x00000038
64 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */
65 DATA 4 0x020E0480 0x00000038
66 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */
67 DATA 4 0x020E0484 0x00000038
68 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */
69 DATA 4 0x020E0488 0x00000038
70 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */
71 DATA 4 0x020E048c 0x00000038
72 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
73 DATA 4 0x020E0464 0x00000038
74 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
75 DATA 4 0x020E0490 0x00000038
76 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
77 DATA 4 0x020E04ac 0x00000038
78 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */
79 DATA 4 0x020E04b0 0x00000038
80 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
81 DATA 4 0x020E0494 0x00000038
82 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 */
83 DATA 4 0x020E04a4 0x00000038
84 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 */
85 DATA 4 0x020E04a8 0x00000038
87 * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
88 * DSE can be configured using Group Control Register:
89 * IOMUXC_SW_PAD_CTL_GRP_CTLDS
91 DATA 4 0x020E04a0 0x00000000
92 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
93 DATA 4 0x020E04b4 0x00000038
94 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
95 DATA 4 0x020E04b8 0x00000038
96 /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
97 DATA 4 0x020E0764 0x00000038
98 /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
99 DATA 4 0x020E0770 0x00000038
100 /* IOMUXC_SW_PAD_CTL_GRP_B2DS */
101 DATA 4 0x020E0778 0x00000038
102 /* IOMUXC_SW_PAD_CTL_GRP_B3DS */
103 DATA 4 0x020E077c 0x00000038
104 /* IOMUXC_SW_PAD_CTL_GRP_B4DS */
105 DATA 4 0x020E0780 0x00000038
106 /* IOMUXC_SW_PAD_CTL_GRP_B5DS */
107 DATA 4 0x020E0784 0x00000038
108 /* IOMUXC_SW_PAD_CTL_GRP_B6DS */
109 DATA 4 0x020E078c 0x00000038
110 /* IOMUXC_SW_PAD_CTL_GRP_B7DS */
111 DATA 4 0x020E0748 0x00000038
112 /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
113 DATA 4 0x020E074c 0x00000038
114 /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
115 DATA 4 0x020E076c 0x00000038
116 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
117 DATA 4 0x020E0750 0x00020000
118 /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
119 DATA 4 0x020E0754 0x00000000
120 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
121 DATA 4 0x020E0760 0x00020000
122 /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
123 DATA 4 0x020E0774 0x00080000
126 * DDR Controller Registers
128 * Manufacturer: Mocron
129 * Device Part Number: MT42L64M64D2KH-18
130 * Clock Freq.: 528MHz
131 * MMDC channels: Both MMDC0, MMDC1
132 *Density per CS in Gb: 256M
133 * Chip Selects used: 2
140 /* MMDC_P0_BASE_ADDR = 0x021b0000 */
141 /* MMDC_P1_BASE_ADDR = 0x021b4000 */
143 /* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
144 DATA 4 0x021b001c 0x00008000
146 /* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
147 DATA 4 0x021b401c 0x00008000
149 /*LPDDR2 ZQ params */
150 DATA 4 0x021b085c 0x1b5f01ff
151 DATA 4 0x021b485c 0x1b5f01ff
153 /* Calibration setup. */
154 /* DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration */
155 DATA 4 0x021b0800 0xa1390003
157 /*ca bus abs delay */
158 DATA 4 0x021b0890 0x00400000
159 /*ca bus abs delay */
160 DATA 4 0x021b4890 0x00400000
161 /* values of 20,40,50,60,7f tried. no difference seen */
163 /* DDR_PHY_P1_MPWRCADL */
164 DATA 4 0x021b48bc 0x00055555
167 DATA 4 0x021b08b8 0x00000800
169 DATA 4 0x021b48b8 0x00000800
171 /* DDR_PHY_P0_MPREDQBY0DL3 */
172 DATA 4 0x021b081c 0x33333333
173 /* DDR_PHY_P0_MPREDQBY1DL3 */
174 DATA 4 0x021b0820 0x33333333
175 /* DDR_PHY_P0_MPREDQBY2DL3 */
176 DATA 4 0x021b0824 0x33333333
177 /* DDR_PHY_P0_MPREDQBY3DL3 */
178 DATA 4 0x021b0828 0x33333333
179 /* DDR_PHY_P1_MPREDQBY0DL3 */
180 DATA 4 0x021b481c 0x33333333
181 /* DDR_PHY_P1_MPREDQBY1DL3 */
182 DATA 4 0x021b4820 0x33333333
183 /* DDR_PHY_P1_MPREDQBY2DL3 */
184 DATA 4 0x021b4824 0x33333333
185 /* DDR_PHY_P1_MPREDQBY3DL3 */
186 DATA 4 0x021b4828 0x33333333
189 * Read and write data delay, per byte.
190 * For optimized DDR operation it is recommended to run mmdc_calibration
191 * on your board, and replace 4 delay register assigns with resulted values
193 * a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section
194 * should be skipped, or the write/read calibration comming after that
196 * b. The calibration code that runs for both MMDC0 & MMDC1 should be used.
199 DATA 4 0x021b0848 0x4b4b524f
200 DATA 4 0x021b4848 0x494f4c44
202 DATA 4 0x021b0850 0x3c3d303c
203 DATA 4 0x021b4850 0x3c343d38
206 DATA 4 0x021b083c 0x20000000
207 DATA 4 0x021b0840 0x0
208 DATA 4 0x021b483c 0x20000000
209 DATA 4 0x021b4840 0x0
212 DATA 4 0x021b0858 0xa00
214 DATA 4 0x021b4858 0xa00
217 DATA 4 0x021b08b8 0x00000800
219 DATA 4 0x021b48b8 0x00000800
220 /* Calibration setup end */
222 /* Channel0 - startng address 0x80000000 */
224 DATA 4 0x021b000c 0x34386145
227 DATA 4 0x021b0004 0x00020036
229 DATA 4 0x021b0010 0x00100c83
231 DATA 4 0x021b0014 0x000000Dc
233 DATA 4 0x021b0018 0x0000174C
235 DATA 4 0x021b002c 0x0f9f26d2
237 DATA 4 0x021b0030 0x0000020e
239 DATA 4 0x021b0038 0x00190778
241 DATA 4 0x021b0008 0x00000000
244 DATA 4 0x021b0040 0x0000005f
246 DATA 4 0x021b0404 0x0000000f
249 DATA 4 0x021b0000 0xc3010000
251 /* Channel1 - starting address 0x10000000 */
253 DATA 4 0x021b400c 0x34386145
256 DATA 4 0x021b4004 0x00020036
258 DATA 4 0x021b4010 0x00100c83
260 DATA 4 0x021b4014 0x000000Dc
262 DATA 4 0x021b4018 0x0000174C
264 DATA 4 0x021b402c 0x0f9f26d2
266 DATA 4 0x021b4030 0x0000020e
268 DATA 4 0x021b4038 0x00190778
270 DATA 4 0x021b4008 0x00000000
273 DATA 4 0x021b4040 0x0000003f
276 DATA 4 0x021b4000 0xc3010000
278 /* Channel0 : Configure DDR device:*/
279 /* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
280 DATA 4 0x021b001c 0x003f8030
281 /* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
282 DATA 4 0x021b001c 0xff0a8030
283 /* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */
284 DATA 4 0x021b001c 0xa2018030
285 /* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
286 DATA 4 0x021b001c 0x06028030
287 /* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */
288 DATA 4 0x021b001c 0x01038030
290 /* Channel1 : Configure DDR device:*/
291 /* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
292 DATA 4 0x021b401c 0x003f8030
293 /* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
294 DATA 4 0x021b401c 0xff0a8030
295 /* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */
296 DATA 4 0x021b401c 0xa2018030
297 /* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
298 DATA 4 0x021b401c 0x06028030
299 /* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */
300 DATA 4 0x021b401c 0x01038030
303 DATA 4 0x021b0020 0x00005800
305 DATA 4 0x021b4020 0x00005800
307 /* DDR_PHY_P0_MPODTCTRL */
308 DATA 4 0x021b0818 0x0
309 /* DDR_PHY_P1_MPODTCTRL */
310 DATA 4 0x021b4818 0x0
313 * calibration values based on calibration compare of 0x00ffff00:
314 * Note, these calibration values are based on Freescale's board
315 * May need to run calibration on target board to fine tune these
318 /* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration */
319 DATA 4 0x021b0800 0xa1310003
321 /* DDR_PHY_P0_MPMUR0, frc_msr */
322 DATA 4 0x021b08b8 0x00000800
323 /* DDR_PHY_P1_MPMUR0, frc_msr */
324 DATA 4 0x021b48b8 0x00000800
327 * MMDC0_MDSCR, clear this register
328 * (especially the configuration bit as initialization is complete)
330 DATA 4 0x021b001c 0x00000000
332 * MMDC0_MDSCR, clear this register
333 * (especially the configuration bit as initialization is complete)
335 DATA 4 0x021b401c 0x00000000
337 DATA 4 0x020c4068 0x00C03F3F
338 DATA 4 0x020c406c 0x0030FC03
339 DATA 4 0x020c4070 0x0FFFC000
340 DATA 4 0x020c4074 0x3FF00000
341 DATA 4 0x020c4078 0x00FFF300
342 DATA 4 0x020c407c 0x0F0000C3
343 DATA 4 0x020c4080 0x000003FF
345 DATA 4 0x020e0010 0xF00000CF
346 DATA 4 0x020e0018 0x007F007F
347 DATA 4 0x020e001c 0x007F007F
349 #else /* CONFIG_MX6DL_LPDDR2 */
351 DATA 4 0x020e0798 0x000c0000
352 DATA 4 0x020e0758 0x00000000
353 DATA 4 0x020e0588 0x00000030
354 DATA 4 0x020e0594 0x00000030
355 DATA 4 0x020e056c 0x00000030
356 DATA 4 0x020e0578 0x00000030
357 DATA 4 0x020e074c 0x00000030
358 DATA 4 0x020e057c 0x00000030
359 DATA 4 0x020e0590 0x00003000
360 DATA 4 0x020e0598 0x00003000
361 DATA 4 0x020e058c 0x00000000
362 DATA 4 0x020e059c 0x00003030
363 DATA 4 0x020e05a0 0x00003030
364 DATA 4 0x020e078c 0x00000030
365 DATA 4 0x020e0750 0x00020000
366 DATA 4 0x020e05a8 0x00000030
367 DATA 4 0x020e05b0 0x00000030
368 DATA 4 0x020e0524 0x00000030
369 DATA 4 0x020e051c 0x00000030
370 DATA 4 0x020e0518 0x00000030
371 DATA 4 0x020e050c 0x00000030
372 DATA 4 0x020e05b8 0x00000030
373 DATA 4 0x020e05c0 0x00000030
374 DATA 4 0x020e0774 0x00020000
375 DATA 4 0x020e0784 0x00000030
376 DATA 4 0x020e0788 0x00000030
377 DATA 4 0x020e0794 0x00000030
378 DATA 4 0x020e079c 0x00000030
379 DATA 4 0x020e07a0 0x00000030
380 DATA 4 0x020e07a4 0x00000030
381 DATA 4 0x020e07a8 0x00000030
382 DATA 4 0x020e0748 0x00000030
383 DATA 4 0x020e05ac 0x00000030
384 DATA 4 0x020e05b4 0x00000030
385 DATA 4 0x020e0528 0x00000030
386 DATA 4 0x020e0520 0x00000030
387 DATA 4 0x020e0514 0x00000030
388 DATA 4 0x020e0510 0x00000030
389 DATA 4 0x020e05bc 0x00000030
390 DATA 4 0x020e05c4 0x00000030
392 DATA 4 0x021b0800 0xa1390003
393 DATA 4 0x021b4800 0xa1390003
394 DATA 4 0x021b080c 0x001F001F
395 DATA 4 0x021b0810 0x001F001F
396 DATA 4 0x021b480c 0x00370037
397 DATA 4 0x021b4810 0x00370037
398 DATA 4 0x021b083c 0x422f0220
399 DATA 4 0x021b0840 0x021f0219
400 DATA 4 0x021b483C 0x422f0220
401 DATA 4 0x021b4840 0x022d022f
402 DATA 4 0x021b0848 0x47494b49
403 DATA 4 0x021b4848 0x48484c47
404 DATA 4 0x021b0850 0x39382b2f
405 DATA 4 0x021b4850 0x2f35312c
406 DATA 4 0x021b081c 0x33333333
407 DATA 4 0x021b0820 0x33333333
408 DATA 4 0x021b0824 0x33333333
409 DATA 4 0x021b0828 0x33333333
410 DATA 4 0x021b481c 0x33333333
411 DATA 4 0x021b4820 0x33333333
412 DATA 4 0x021b4824 0x33333333
413 DATA 4 0x021b4828 0x33333333
414 DATA 4 0x021b08b8 0x00000800
415 DATA 4 0x021b48b8 0x00000800
416 DATA 4 0x021b0004 0x0002002d
417 DATA 4 0x021b0008 0x00333030
419 DATA 4 0x021b000c 0x40445323
420 DATA 4 0x021b0010 0xb66e8c63
422 DATA 4 0x021b0014 0x01ff00db
423 DATA 4 0x021b0018 0x00081740
424 DATA 4 0x021b001c 0x00008000
425 DATA 4 0x021b002c 0x000026d2
426 DATA 4 0x021b0030 0x00440e21
427 #ifdef CONFIG_DDR_32BIT
428 DATA 4 0x021b0040 0x00000017
429 DATA 4 0x021b0000 0xc3190000
431 DATA 4 0x021b0040 0x00000027
432 DATA 4 0x021b0000 0xc31a0000
434 DATA 4 0x021b001c 0x04008032
435 DATA 4 0x021b001c 0x0400803a
436 DATA 4 0x021b001c 0x00008033
437 DATA 4 0x021b001c 0x0000803b
438 DATA 4 0x021b001c 0x00428031
439 DATA 4 0x021b001c 0x00428039
440 DATA 4 0x021b001c 0x07208030
441 DATA 4 0x021b001c 0x07208038
442 DATA 4 0x021b001c 0x04008040
443 DATA 4 0x021b001c 0x04008048
444 DATA 4 0x021b0020 0x00005800
445 DATA 4 0x021b0818 0x00000007
446 DATA 4 0x021b4818 0x00000007
447 DATA 4 0x021b0004 0x0002556d
448 DATA 4 0x021b4004 0x00011006
449 DATA 4 0x021b001c 0x00000000
451 DATA 4 0x020c4068 0x00C03F3F
452 DATA 4 0x020c406c 0x0030FC03
453 DATA 4 0x020c4070 0x0FFFC000
454 DATA 4 0x020c4074 0x3FF00000
455 DATA 4 0x020c4078 0x00FFF300
456 DATA 4 0x020c407c 0x0F0000C3
457 DATA 4 0x020c4080 0x000003FF
459 DATA 4 0x020e0010 0xF00000CF
460 DATA 4 0x020e0018 0x007F007F
461 DATA 4 0x020e001c 0x007F007F
462 #endif /* CONFIG_MX6DL_LPDDR2 */