2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/mx6-pins.h>
11 #include <asm/arch/clock.h>
12 #include <asm/errno.h>
14 #include <asm/imx-common/iomux-v3.h>
16 #include <fsl_esdhc.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
24 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
25 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
27 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
28 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
29 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
31 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
32 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
36 #if defined(CONFIG_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \
37 defined(CONFIG_DDR_32BIT)
38 gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024) / 2;
40 gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
46 iomux_v3_cfg_t const uart4_pads[] = {
47 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
48 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
51 iomux_v3_cfg_t const usdhc3_pads[] = {
52 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
53 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
54 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
55 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
56 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
57 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
58 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
59 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
60 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
61 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
62 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
65 iomux_v3_cfg_t const usdhc4_pads[] = {
66 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
67 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
68 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
69 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
70 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
71 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
72 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
73 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
74 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
75 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
78 iomux_v3_cfg_t const enet_pads[] = {
79 MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
80 MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
83 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
84 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
85 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
86 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
87 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
88 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
89 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
90 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
91 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
92 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
93 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
97 static void setup_iomux_uart(void)
99 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
102 static void setup_iomux_enet(void)
104 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
107 #ifdef CONFIG_FSL_ESDHC
108 struct fsl_esdhc_cfg usdhc_cfg[2] = {
113 int board_mmc_get_env_dev(int devno)
118 int board_mmc_getcd(struct mmc *mmc)
120 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
123 if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
124 gpio_direction_input(IMX_GPIO_NR(6, 11));
125 ret = !gpio_get_value(IMX_GPIO_NR(6, 11));
126 } else /* Don't have the CD GPIO pin on board */
132 int board_mmc_init(bd_t *bis)
137 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
138 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
140 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
143 imx_iomux_v3_setup_multiple_pads(
144 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
147 imx_iomux_v3_setup_multiple_pads(
148 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
151 printf("Warning: you configured more USDHC controllers"
152 "(%d) then supported by the board (%d)\n",
153 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
157 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
166 #define MII_MMD_ACCESS_CTRL_REG 0xd
167 #define MII_MMD_ACCESS_ADDR_DATA_REG 0xe
168 #define MII_DBG_PORT_REG 0x1d
169 #define MII_DBG_PORT2_REG 0x1e
171 int fecmxc_mii_postcall(int phy)
176 * Due to the i.MX6Q Armadillo2 board HW design,there is
177 * no 125Mhz clock input from SOC. In order to use RGMII,
178 * We need enable AR8031 ouput a 125MHz clk from CLK_25M
180 miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7);
181 miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016);
182 miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007);
183 miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val);
186 miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val);
188 /* For the RGMII phy, we need enable tx clock delay */
189 miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5);
190 miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val);
192 miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val);
194 miiphy_write("FEC", phy, MII_BMCR, 0xa100);
199 int board_eth_init(bd_t *bis)
201 struct eth_device *dev;
202 int ret = cpu_eth_init(bis);
207 dev = eth_get_dev_by_name("FEC");
209 printf("FEC MXC: Unable to get FEC device entry\n");
213 ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
215 printf("FEC MXC: Unable to register FEC mii postcall\n");
222 #ifdef CONFIG_USB_EHCI_MX6
223 #define USB_OTHERREGS_OFFSET 0x800
224 #define UCTRL_PWR_POL (1 << 9)
226 static iomux_v3_cfg_t const usb_otg_pads[] = {
227 MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
228 MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
231 static void setup_usb(void)
233 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
234 ARRAY_SIZE(usb_otg_pads));
237 * set daisy chain for otg_pin_id on 6q.
238 * for 6dl, this bit is reserved
240 imx_iomux_set_gpr_register(1, 13, 1, 1);
243 int board_ehci_hcd_init(int port)
250 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
253 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
259 int board_early_init_f(void)
269 /* address of boot parameters */
270 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
272 #ifdef CONFIG_USB_EHCI_MX6
282 puts("Board: MX6DL-Armadillo2\n");
284 puts("Board: MX6Q-Armadillo2\n");