git.sur5r.net Git - u-boot/blob - board/freescale/mx6qsabreauto/mx6qsabreauto.c

   1 /*
   2  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/errno.h>
  16 #include <asm/gpio.h>
  17 #include <asm/imx-common/iomux-v3.h>
  18 #include <asm/imx-common/mxc_i2c.h>
  19 #include <asm/imx-common/boot_mode.h>
  20 #include <asm/imx-common/spi.h>
  21 #include <mmc.h>
  22 #include <fsl_esdhc.h>
  23 #include <miiphy.h>
  24 #include <netdev.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <i2c.h>
  27 #include <asm/arch/mxc_hdmi.h>
  28 #include <asm/imx-common/video.h>
  29 #include <asm/arch/crm_regs.h>
  30 #include <pca953x.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  35         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  36         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  37
  38 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  39         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  40         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  41
  42 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  43         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  44
  45 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  46         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  47         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  48
  49 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  50 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  51                         PAD_CTL_SRE_FAST)
  52 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  53
  54 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  55
  56 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |          \
  57         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  58         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
  59
  60 int dram_init(void)
  61 {
  62         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  63
  64         return 0;
  65 }
  66
  67 static iomux_v3_cfg_t const uart4_pads[] = {
  68         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  69         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  70 };
  71
  72 static iomux_v3_cfg_t const enet_pads[] = {
  73         MX6_PAD_KEY_COL1__ENET_MDIO             | MUX_PAD_CTRL(ENET_PAD_CTRL),
  74         MX6_PAD_KEY_COL2__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
  75         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  76         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  77         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  78         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  79         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  80         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  81         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  82         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  83         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  84         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  85         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  86         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  87         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88 };
  89
  90 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
  91 static struct i2c_pads_info i2c_pad_info1 = {
  92         .scl = {
  93                 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
  94                 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
  95                 .gp = IMX_GPIO_NR(2, 30)
  96         },
  97         .sda = {
  98                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
  99                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 100                 .gp = IMX_GPIO_NR(4, 13)
 101         }
 102 };
 103
 104 #ifndef CONFIG_SYS_FLASH_CFI
 105 /*
 106  * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
 107  * Compass Sensor, Accelerometer, Res Touch
 108  */
 109 static struct i2c_pads_info i2c_pad_info2 = {
 110         .scl = {
 111                 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
 112                 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
 113                 .gp = IMX_GPIO_NR(1, 3)
 114         },
 115         .sda = {
 116                 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
 117                 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
 118                 .gp = IMX_GPIO_NR(3, 18)
 119         }
 120 };
 121 #endif
 122
 123 static iomux_v3_cfg_t const i2c3_pads[] = {
 124         MX6_PAD_EIM_A24__GPIO5_IO04             | MUX_PAD_CTRL(NO_PAD_CTRL),
 125 };
 126
 127 static iomux_v3_cfg_t const port_exp[] = {
 128         MX6_PAD_SD2_DAT0__GPIO1_IO15            | MUX_PAD_CTRL(NO_PAD_CTRL),
 129 };
 130
 131 /*Define for building port exp gpio, pin starts from 0*/
 132 #define PORTEXP_IO_NR(chip, pin) \
 133         ((chip << 5) + pin)
 134
 135 /*Get the chip addr from a ioexp gpio*/
 136 #define PORTEXP_IO_TO_CHIP(gpio_nr) \
 137         (gpio_nr >> 5)
 138
 139 /*Get the pin number from a ioexp gpio*/
 140 #define PORTEXP_IO_TO_PIN(gpio_nr) \
 141         (gpio_nr & 0x1f)
 142
 143 static int port_exp_direction_output(unsigned gpio, int value)
 144 {
 145         int ret;
 146
 147         i2c_set_bus_num(2);
 148         ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
 149         if (ret)
 150                 return ret;
 151
 152         ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
 153                 (1 << PORTEXP_IO_TO_PIN(gpio)),
 154                 (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
 155
 156         if (ret)
 157                 return ret;
 158
 159         ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
 160                 (1 << PORTEXP_IO_TO_PIN(gpio)),
 161                 (value << PORTEXP_IO_TO_PIN(gpio)));
 162
 163         if (ret)
 164                 return ret;
 165
 166         return 0;
 167 }
 168
 169 static iomux_v3_cfg_t const eimnor_pads[] = {
 170         MX6_PAD_EIM_D16__EIM_DATA16     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 171         MX6_PAD_EIM_D17__EIM_DATA17     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 172         MX6_PAD_EIM_D18__EIM_DATA18     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 173         MX6_PAD_EIM_D19__EIM_DATA19     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 174         MX6_PAD_EIM_D20__EIM_DATA20     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 175         MX6_PAD_EIM_D21__EIM_DATA21     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 176         MX6_PAD_EIM_D22__EIM_DATA22     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 177         MX6_PAD_EIM_D23__EIM_DATA23     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 178         MX6_PAD_EIM_D24__EIM_DATA24     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 179         MX6_PAD_EIM_D25__EIM_DATA25     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 180         MX6_PAD_EIM_D26__EIM_DATA26     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 181         MX6_PAD_EIM_D27__EIM_DATA27     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 182         MX6_PAD_EIM_D28__EIM_DATA28     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 183         MX6_PAD_EIM_D29__EIM_DATA29     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 184         MX6_PAD_EIM_D30__EIM_DATA30     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 185         MX6_PAD_EIM_D31__EIM_DATA31     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 186         MX6_PAD_EIM_DA0__EIM_AD00       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 187         MX6_PAD_EIM_DA1__EIM_AD01       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 188         MX6_PAD_EIM_DA2__EIM_AD02       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 189         MX6_PAD_EIM_DA3__EIM_AD03       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 190         MX6_PAD_EIM_DA4__EIM_AD04       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 191         MX6_PAD_EIM_DA5__EIM_AD05       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 192         MX6_PAD_EIM_DA6__EIM_AD06       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 193         MX6_PAD_EIM_DA7__EIM_AD07       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 194         MX6_PAD_EIM_DA8__EIM_AD08       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 195         MX6_PAD_EIM_DA9__EIM_AD09       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 196         MX6_PAD_EIM_DA10__EIM_AD10      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 197         MX6_PAD_EIM_DA11__EIM_AD11      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
 198         MX6_PAD_EIM_DA12__EIM_AD12      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 199         MX6_PAD_EIM_DA13__EIM_AD13      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 200         MX6_PAD_EIM_DA14__EIM_AD14      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 201         MX6_PAD_EIM_DA15__EIM_AD15      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 202         MX6_PAD_EIM_A16__EIM_ADDR16     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 203         MX6_PAD_EIM_A17__EIM_ADDR17     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 204         MX6_PAD_EIM_A18__EIM_ADDR18     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 205         MX6_PAD_EIM_A19__EIM_ADDR19     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 206         MX6_PAD_EIM_A20__EIM_ADDR20     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 207         MX6_PAD_EIM_A21__EIM_ADDR21     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 208         MX6_PAD_EIM_A22__EIM_ADDR22     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 209         MX6_PAD_EIM_A23__EIM_ADDR23     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 210         MX6_PAD_EIM_OE__EIM_OE_B        | MUX_PAD_CTRL(NO_PAD_CTRL),
 211         MX6_PAD_EIM_RW__EIM_RW          | MUX_PAD_CTRL(NO_PAD_CTRL),
 212         MX6_PAD_EIM_CS0__EIM_CS0_B      | MUX_PAD_CTRL(NO_PAD_CTRL),
 213 };
 214
 215 static void eimnor_cs_setup(void)
 216 {
 217         struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
 218
 219         writel(0x00020181, &weim_regs->cs0gcr1);
 220         writel(0x00000001, &weim_regs->cs0gcr2);
 221         writel(0x0a020000, &weim_regs->cs0rcr1);
 222         writel(0x0000c000, &weim_regs->cs0rcr2);
 223         writel(0x0804a240, &weim_regs->cs0wcr1);
 224         writel(0x00000120, &weim_regs->wcr);
 225
 226         set_chipselect_size(CS0_128);
 227 }
 228
 229 static void setup_iomux_eimnor(void)
 230 {
 231         imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
 232
 233         gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
 234
 235         eimnor_cs_setup();
 236 }
 237
 238 static void setup_iomux_enet(void)
 239 {
 240         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 241 }
 242
 243 static iomux_v3_cfg_t const usdhc3_pads[] = {
 244         MX6_PAD_SD3_CLK__SD3_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 245         MX6_PAD_SD3_CMD__SD3_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 246         MX6_PAD_SD3_DAT0__SD3_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 247         MX6_PAD_SD3_DAT1__SD3_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 248         MX6_PAD_SD3_DAT2__SD3_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 249         MX6_PAD_SD3_DAT3__SD3_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 250         MX6_PAD_SD3_DAT4__SD3_DATA4     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 251         MX6_PAD_SD3_DAT5__SD3_DATA5     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 252         MX6_PAD_SD3_DAT6__SD3_DATA6     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 253         MX6_PAD_SD3_DAT7__SD3_DATA7     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 254         MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 255         MX6_PAD_NANDF_CS2__GPIO6_IO15   | MUX_PAD_CTRL(NO_PAD_CTRL),
 256 };
 257
 258 static void setup_iomux_uart(void)
 259 {
 260         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 261 }
 262
 263 #ifdef CONFIG_FSL_ESDHC
 264 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 265         {USDHC3_BASE_ADDR},
 266 };
 267
 268 int board_mmc_getcd(struct mmc *mmc)
 269 {
 270         gpio_direction_input(IMX_GPIO_NR(6, 15));
 271         return !gpio_get_value(IMX_GPIO_NR(6, 15));
 272 }
 273
 274 int board_mmc_init(bd_t *bis)
 275 {
 276         imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 277
 278         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 279         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 280 }
 281 #endif
 282
 283 #ifdef CONFIG_NAND_MXS
 284 static iomux_v3_cfg_t gpmi_pads[] = {
 285         MX6_PAD_NANDF_CLE__NAND_CLE             | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 286         MX6_PAD_NANDF_ALE__NAND_ALE             | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 287         MX6_PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 288         MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
 289         MX6_PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 290         MX6_PAD_SD4_CMD__NAND_RE_B              | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 291         MX6_PAD_SD4_CLK__NAND_WE_B              | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 292         MX6_PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 293         MX6_PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 294         MX6_PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 295         MX6_PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 296         MX6_PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 297         MX6_PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 298         MX6_PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 299         MX6_PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 300         MX6_PAD_SD4_DAT0__NAND_DQS              | MUX_PAD_CTRL(GPMI_PAD_CTRL1),
 301 };
 302
 303 static void setup_gpmi_nand(void)
 304 {
 305         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 306
 307         /* config gpmi nand iomux */
 308         imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
 309
 310         /* gate ENFC_CLK_ROOT clock first,before clk source switch */
 311         clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 312         clrbits_le32(&mxc_ccm->CCGR4,
 313                 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 314
 315         /* config gpmi and bch clock to 100 MHz */
 316         clrsetbits_le32(&mxc_ccm->cs2cdr,
 317                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 318                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 319                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 320                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 321                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 322                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 323
 324         /* enable ENFC_CLK_ROOT clock */
 325         setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 326
 327         /* enable gpmi and bch clock gating */
 328         setbits_le32(&mxc_ccm->CCGR4,
 329                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 330                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 331                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 332                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 333                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 334
 335         /* enable apbh clock gating */
 336         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 337 }
 338 #endif
 339
 340 int mx6_rgmii_rework(struct phy_device *phydev)
 341 {
 342         unsigned short val;
 343
 344         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 345         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 346         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 347         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 348
 349         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 350         val &= 0xffe3;
 351         val |= 0x18;
 352         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 353
 354         /* introduce tx clock delay */
 355         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 356         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 357         val |= 0x0100;
 358         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 359
 360         return 0;
 361 }
 362
 363 int board_phy_config(struct phy_device *phydev)
 364 {
 365         mx6_rgmii_rework(phydev);
 366
 367         if (phydev->drv->config)
 368                 phydev->drv->config(phydev);
 369
 370         return 0;
 371 }
 372
 373 int board_eth_init(bd_t *bis)
 374 {
 375         setup_iomux_enet();
 376
 377         return cpu_eth_init(bis);
 378 }
 379
 380 #define BOARD_REV_B  0x200
 381 #define BOARD_REV_A  0x100
 382
 383 static int mx6sabre_rev(void)
 384 {
 385         /*
 386          * Get Board ID information from OCOTP_GP1[15:8]
 387          * i.MX6Q ARD RevA: 0x01
 388          * i.MX6Q ARD RevB: 0x02
 389          */
 390         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 391         struct fuse_bank *bank = &ocotp->bank[4];
 392         struct fuse_bank4_regs *fuse =
 393                         (struct fuse_bank4_regs *)bank->fuse_regs;
 394         int reg = readl(&fuse->gp1);
 395         int ret;
 396
 397         switch (reg >> 8 & 0x0F) {
 398         case 0x02:
 399                 ret = BOARD_REV_B;
 400                 break;
 401         case 0x01:
 402         default:
 403                 ret = BOARD_REV_A;
 404                 break;
 405         }
 406
 407         return ret;
 408 }
 409
 410 u32 get_board_rev(void)
 411 {
 412         int rev = mx6sabre_rev();
 413
 414         return (get_cpu_rev() & ~(0xF << 8)) | rev;
 415 }
 416
 417 #if defined(CONFIG_VIDEO_IPUV3)
 418 static void do_enable_hdmi(struct display_info_t const *dev)
 419 {
 420         imx_enable_hdmi_phy();
 421 }
 422
 423 struct display_info_t const displays[] = {{
 424         .bus    = -1,
 425         .addr   = 0,
 426         .pixfmt = IPU_PIX_FMT_RGB24,
 427         .detect = detect_hdmi,
 428         .enable = do_enable_hdmi,
 429         .mode   = {
 430                 .name           = "HDMI",
 431                 .refresh        = 60,
 432                 .xres           = 1024,
 433                 .yres           = 768,
 434                 .pixclock       = 15385,
 435                 .left_margin    = 220,
 436                 .right_margin   = 40,
 437                 .upper_margin   = 21,
 438                 .lower_margin   = 7,
 439                 .hsync_len      = 60,
 440                 .vsync_len      = 10,
 441                 .sync           = FB_SYNC_EXT,
 442                 .vmode          = FB_VMODE_NONINTERLACED,
 443 } } };
 444 size_t display_count = ARRAY_SIZE(displays);
 445
 446 static void setup_display(void)
 447 {
 448         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 449         int reg;
 450
 451         enable_ipu_clock();
 452         imx_setup_hdmi();
 453
 454         reg = readl(&mxc_ccm->chsccdr);
 455         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 456                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 457         writel(reg, &mxc_ccm->chsccdr);
 458 }
 459 #endif /* CONFIG_VIDEO_IPUV3 */
 460
 461 /*
 462  * Do not overwrite the console
 463  * Use always serial for U-Boot console
 464  */
 465 int overwrite_console(void)
 466 {
 467         return 1;
 468 }
 469
 470 int board_early_init_f(void)
 471 {
 472         setup_iomux_uart();
 473 #ifdef CONFIG_VIDEO_IPUV3
 474         setup_display();
 475 #endif
 476
 477 #ifdef CONFIG_NAND_MXS
 478         setup_gpmi_nand();
 479 #endif
 480
 481         return 0;
 482 }
 483
 484 int board_init(void)
 485 {
 486         /* address of boot parameters */
 487         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 488
 489         /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
 490         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 491         /* I2C 3 Steer */
 492         gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
 493         imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
 494 #ifndef CONFIG_SYS_FLASH_CFI
 495         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 496 #endif
 497         gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
 498         imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
 499
 500         setup_iomux_eimnor();
 501         return 0;
 502 }
 503
 504 #ifdef CONFIG_MXC_SPI
 505 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 506 {
 507         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
 508 }
 509 #endif
 510
 511 #ifdef CONFIG_CMD_BMODE
 512 static const struct boot_mode board_boot_modes[] = {
 513         /* 4 bit bus width */
 514         {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 515         {NULL,   0},
 516 };
 517 #endif
 518
 519 int board_late_init(void)
 520 {
 521 #ifdef CONFIG_CMD_BMODE
 522         add_board_boot_modes(board_boot_modes);
 523 #endif
 524
 525         return 0;
 526 }
 527
 528 int checkboard(void)
 529 {
 530         int rev = mx6sabre_rev();
 531         char *revname;
 532
 533         switch (rev) {
 534         case BOARD_REV_B:
 535                 revname = "B";
 536                 break;
 537         case BOARD_REV_A:
 538         default:
 539                 revname = "A";
 540                 break;
 541         }
 542
 543         printf("Board: MX6Q-Sabreauto rev%s\n", revname);
 544
 545         return 0;
 546 }
 547
 548 #ifdef CONFIG_USB_EHCI_MX6
 549 #define USB_HOST1_PWR     PORTEXP_IO_NR(0x32, 7)
 550 #define USB_OTG_PWR       PORTEXP_IO_NR(0x34, 1)
 551
 552 iomux_v3_cfg_t const usb_otg_pads[] = {
 553         MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
 554 };
 555
 556 int board_ehci_hcd_init(int port)
 557 {
 558         switch (port) {
 559         case 0:
 560                 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 561                         ARRAY_SIZE(usb_otg_pads));
 562
 563                 /*
 564                   * Set daisy chain for otg_pin_id on 6q.
 565                  *  For 6dl, this bit is reserved.
 566                  */
 567                 imx_iomux_set_gpr_register(1, 13, 1, 0);
 568                 break;
 569         case 1:
 570                 break;
 571         default:
 572                 printf("MXC USB port %d not yet supported\n", port);
 573                 return -EINVAL;
 574         }
 575         return 0;
 576 }
 577
 578 int board_ehci_power(int port, int on)
 579 {
 580         switch (port) {
 581         case 0:
 582                 if (on)
 583                         port_exp_direction_output(USB_OTG_PWR, 1);
 584                 else
 585                         port_exp_direction_output(USB_OTG_PWR, 0);
 586                 break;
 587         case 1:
 588                 if (on)
 589                         port_exp_direction_output(USB_HOST1_PWR, 1);
 590                 else
 591                         port_exp_direction_output(USB_HOST1_PWR, 0);
 592                 break;
 593         default:
 594                 printf("MXC USB port %d not yet supported\n", port);
 595                 return -EINVAL;
 596         }
 597
 598         return 0;
 599 }
 600 #endif