2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/mx6x_pins.h>
27 #include <asm/arch/iomux-v3.h>
28 #include <asm/errno.h>
31 #include <fsl_esdhc.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
38 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
39 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
41 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
42 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
43 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
45 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
46 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
47 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
51 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
56 iomux_v3_cfg_t uart1_pads[] = {
57 MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
58 MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
61 iomux_v3_cfg_t uart2_pads[] = {
62 MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
63 MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
66 iomux_v3_cfg_t usdhc3_pads[] = {
67 MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
68 MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
69 MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
70 MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
71 MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
72 MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
73 MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
76 iomux_v3_cfg_t usdhc4_pads[] = {
77 MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
78 MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
79 MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
80 MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
81 MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
82 MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
83 MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
86 iomux_v3_cfg_t enet_pads1[] = {
87 MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
88 MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
89 MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
90 MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
91 MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
92 MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
93 MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
94 MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
95 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
96 /* pin 35 - 1 (PHY_AD2) on reset */
97 MX6Q_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL),
98 /* pin 32 - 1 - (MODE0) all */
99 MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
100 /* pin 31 - 1 - (MODE1) all */
101 MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
102 /* pin 28 - 1 - (MODE2) all */
103 MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL),
104 /* pin 27 - 1 - (MODE3) all */
105 MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
106 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
107 MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
108 /* pin 42 PHY nRST */
109 MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
112 iomux_v3_cfg_t enet_pads2[] = {
113 MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
114 MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
115 MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
116 MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
117 MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
118 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
121 static void setup_iomux_enet(void)
123 gpio_direction_output(87, 0); /* GPIO 3-23 */
124 gpio_direction_output(190, 1); /* GPIO 6-30 */
125 gpio_direction_output(185, 1); /* GPIO 6-25 */
126 gpio_direction_output(187, 1); /* GPIO 6-27 */
127 gpio_direction_output(188, 1); /* GPIO 6-28*/
128 gpio_direction_output(189, 1); /* GPIO 6-29 */
129 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
130 gpio_direction_output(184, 1); /* GPIO 6-24 */
132 /* Need delay 10ms according to KSZ9021 spec */
134 gpio_direction_output(87, 1); /* GPIO 3-23 */
136 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
139 static void setup_iomux_uart(void)
141 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
142 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
145 #ifdef CONFIG_FSL_ESDHC
146 struct fsl_esdhc_cfg usdhc_cfg[2] = {
147 {USDHC3_BASE_ADDR, 1},
148 {USDHC4_BASE_ADDR, 1},
151 int board_mmc_getcd(struct mmc *mmc)
153 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
156 if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
157 gpio_direction_input(192); /*GPIO7_0*/
158 ret = !gpio_get_value(192);
160 gpio_direction_input(38); /*GPIO2_6*/
161 ret = !gpio_get_value(38);
167 int board_mmc_init(bd_t *bis)
172 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
175 imx_iomux_v3_setup_multiple_pads(
176 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
179 imx_iomux_v3_setup_multiple_pads(
180 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
183 printf("Warning: you configured more USDHC controllers"
184 "(%d) then supported by the board (%d)\n",
185 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
189 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
196 #define MII_1000BASET_CTRL 0x9
197 #define MII_EXTENDED_CTRL 0xb
198 #define MII_EXTENDED_DATAW 0xc
200 int fecmxc_mii_postcall(int phy)
202 /* prefer master mode */
203 miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x0f00);
205 /* min rx data delay */
206 miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8105);
207 miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000);
209 /* max rx/tx clock delay, min rx/tx control delay */
210 miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8104);
211 miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0xf0f0);
212 miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x104);
217 int board_eth_init(bd_t *bis)
219 struct eth_device *dev;
224 ret = cpu_eth_init(bis);
226 printf("FEC MXC: %s:failed\n", __func__);
230 dev = eth_get_dev_by_name("FEC");
232 printf("FEC MXC: Unable to get FEC device entry\n");
236 ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
238 printf("FEC MXC: Unable to register FEC mii postcall\n");
245 int board_early_init_f(void)
254 /* address of boot parameters */
255 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
262 puts("Board: MX6Q-Sabre Lite\n");