git.sur5r.net Git - u-boot/blob - board/freescale/mx6sabresd/mx6sabresd.c

   1 /*
   2  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <asm/errno.h>
  14 #include <asm/gpio.h>
  15 #include <asm/imx-common/iomux-v3.h>
  16 #include <asm/imx-common/boot_mode.h>
  17 #include <mmc.h>
  18 #include <fsl_esdhc.h>
  19 #include <miiphy.h>
  20 #include <netdev.h>
  21 #include <asm/arch/mxc_hdmi.h>
  22 #include <asm/arch/crm_regs.h>
  23 #include <linux/fb.h>
  24 #include <ipu_pixfmt.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/sys_proto.h>
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  30         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  31         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  32
  33 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  34         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  35         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  36
  37 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  38         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  39
  40 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  41                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  42
  43 int dram_init(void)
  44 {
  45         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  46
  47         return 0;
  48 }
  49
  50 iomux_v3_cfg_t const uart1_pads[] = {
  51         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  52         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  53 };
  54
  55 iomux_v3_cfg_t const enet_pads[] = {
  56         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  57         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
  58         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  59         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  60         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  61         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  62         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  63         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  64         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  65         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  66         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  67         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  68         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  69         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  70         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  71         /* AR8031 PHY Reset */
  72         MX6_PAD_ENET_CRS_DV__GPIO1_IO25         | MUX_PAD_CTRL(NO_PAD_CTRL),
  73 };
  74
  75 static void setup_iomux_enet(void)
  76 {
  77         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  78
  79         /* Reset AR8031 PHY */
  80         gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
  81         udelay(500);
  82         gpio_set_value(IMX_GPIO_NR(1, 25), 1);
  83 }
  84
  85 iomux_v3_cfg_t const usdhc2_pads[] = {
  86         MX6_PAD_SD2_CLK__SD2_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87         MX6_PAD_SD2_CMD__SD2_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88         MX6_PAD_SD2_DAT0__SD2_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  89         MX6_PAD_SD2_DAT1__SD2_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  90         MX6_PAD_SD2_DAT2__SD2_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  91         MX6_PAD_SD2_DAT3__SD2_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  92         MX6_PAD_NANDF_D4__SD2_DATA4     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  93         MX6_PAD_NANDF_D5__SD2_DATA5     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  94         MX6_PAD_NANDF_D6__SD2_DATA6     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  95         MX6_PAD_NANDF_D7__SD2_DATA7     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96         MX6_PAD_NANDF_D2__GPIO2_IO02    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  97 };
  98
  99 iomux_v3_cfg_t const usdhc3_pads[] = {
 100         MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 101         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 102         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 103         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 104         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 105         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 106         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 107         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 108         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 109         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 110         MX6_PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 111 };
 112
 113 iomux_v3_cfg_t const usdhc4_pads[] = {
 114         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 115         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 116         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 117         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 118         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 119         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 120         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 121         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 122         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 123         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 124 };
 125
 126 iomux_v3_cfg_t const ecspi1_pads[] = {
 127         MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 128         MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 129         MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 130         MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
 131 };
 132
 133 static void setup_spi(void)
 134 {
 135         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 136 }
 137
 138 iomux_v3_cfg_t const di0_pads[] = {
 139         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,        /* DISP0_CLK */
 140         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,               /* DISP0_HSYNC */
 141         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,               /* DISP0_VSYNC */
 142 };
 143
 144 static void setup_iomux_uart(void)
 145 {
 146         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 147 }
 148
 149 #ifdef CONFIG_FSL_ESDHC
 150 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 151         {USDHC2_BASE_ADDR},
 152         {USDHC3_BASE_ADDR},
 153         {USDHC4_BASE_ADDR},
 154 };
 155
 156 #define USDHC2_CD_GPIO  IMX_GPIO_NR(2, 2)
 157 #define USDHC3_CD_GPIO  IMX_GPIO_NR(2, 0)
 158
 159 int board_mmc_getcd(struct mmc *mmc)
 160 {
 161         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 162         int ret = 0;
 163
 164         switch (cfg->esdhc_base) {
 165         case USDHC2_BASE_ADDR:
 166                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 167                 break;
 168         case USDHC3_BASE_ADDR:
 169                 ret = !gpio_get_value(USDHC3_CD_GPIO);
 170                 break;
 171         case USDHC4_BASE_ADDR:
 172                 ret = 1; /* eMMC/uSDHC4 is always present */
 173                 break;
 174         }
 175
 176         return ret;
 177 }
 178
 179 int board_mmc_init(bd_t *bis)
 180 {
 181         s32 status = 0;
 182         int i;
 183
 184         /*
 185          * According to the board_mmc_init() the following map is done:
 186          * (U-boot device node)    (Physical Port)
 187          * mmc0                    SD2
 188          * mmc1                    SD3
 189          * mmc2                    eMMC
 190          */
 191         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 192                 switch (i) {
 193                 case 0:
 194                         imx_iomux_v3_setup_multiple_pads(
 195                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 196                         gpio_direction_input(USDHC2_CD_GPIO);
 197                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 198                         break;
 199                 case 1:
 200                         imx_iomux_v3_setup_multiple_pads(
 201                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 202                         gpio_direction_input(USDHC3_CD_GPIO);
 203                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 204                         break;
 205                 case 2:
 206                         imx_iomux_v3_setup_multiple_pads(
 207                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 208                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 209                         break;
 210                 default:
 211                         printf("Warning: you configured more USDHC controllers"
 212                                "(%d) then supported by the board (%d)\n",
 213                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 214                         return status;
 215                 }
 216
 217                 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 218         }
 219
 220         return status;
 221 }
 222 #endif
 223
 224 int mx6_rgmii_rework(struct phy_device *phydev)
 225 {
 226         unsigned short val;
 227
 228         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 229         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 230         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 231         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 232
 233         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 234         val &= 0xffe3;
 235         val |= 0x18;
 236         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 237
 238         /* introduce tx clock delay */
 239         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 240         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 241         val |= 0x0100;
 242         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 243
 244         return 0;
 245 }
 246
 247 int board_phy_config(struct phy_device *phydev)
 248 {
 249         mx6_rgmii_rework(phydev);
 250
 251         if (phydev->drv->config)
 252                 phydev->drv->config(phydev);
 253
 254         return 0;
 255 }
 256
 257 #if defined(CONFIG_VIDEO_IPUV3)
 258 struct display_info_t {
 259         int     bus;
 260         int     addr;
 261         int     pixfmt;
 262         int     (*detect)(struct display_info_t const *dev);
 263         void    (*enable)(struct display_info_t const *dev);
 264         struct  fb_videomode mode;
 265 };
 266
 267 static int detect_hdmi(struct display_info_t const *dev)
 268 {
 269         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 270         return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
 271 }
 272
 273
 274 static void disable_lvds(struct display_info_t const *dev)
 275 {
 276         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 277
 278         int reg = readl(&iomux->gpr[2]);
 279
 280         reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
 281                  IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
 282
 283         writel(reg, &iomux->gpr[2]);
 284 }
 285
 286 static void do_enable_hdmi(struct display_info_t const *dev)
 287 {
 288         disable_lvds(dev);
 289         imx_enable_hdmi_phy();
 290 }
 291
 292 static void enable_lvds(struct display_info_t const *dev)
 293 {
 294         struct iomuxc *iomux = (struct iomuxc *)
 295                                 IOMUXC_BASE_ADDR;
 296         u32 reg = readl(&iomux->gpr[2]);
 297         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
 298                IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
 299         writel(reg, &iomux->gpr[2]);
 300 }
 301
 302 static struct display_info_t const displays[] = {{
 303         .bus    = -1,
 304         .addr   = 0,
 305         .pixfmt = IPU_PIX_FMT_RGB666,
 306         .detect = NULL,
 307         .enable = enable_lvds,
 308         .mode   = {
 309                 .name           = "Hannstar-XGA",
 310                 .refresh        = 60,
 311                 .xres           = 1024,
 312                 .yres           = 768,
 313                 .pixclock       = 15385,
 314                 .left_margin    = 220,
 315                 .right_margin   = 40,
 316                 .upper_margin   = 21,
 317                 .lower_margin   = 7,
 318                 .hsync_len      = 60,
 319                 .vsync_len      = 10,
 320                 .sync           = FB_SYNC_EXT,
 321                 .vmode          = FB_VMODE_NONINTERLACED
 322 } }, {
 323         .bus    = -1,
 324         .addr   = 0,
 325         .pixfmt = IPU_PIX_FMT_RGB24,
 326         .detect = detect_hdmi,
 327         .enable = do_enable_hdmi,
 328         .mode   = {
 329                 .name           = "HDMI",
 330                 .refresh        = 60,
 331                 .xres           = 1024,
 332                 .yres           = 768,
 333                 .pixclock       = 15385,
 334                 .left_margin    = 220,
 335                 .right_margin   = 40,
 336                 .upper_margin   = 21,
 337                 .lower_margin   = 7,
 338                 .hsync_len      = 60,
 339                 .vsync_len      = 10,
 340                 .sync           = FB_SYNC_EXT,
 341                 .vmode          = FB_VMODE_NONINTERLACED
 342 } } };
 343
 344 int board_video_skip(void)
 345 {
 346         int i;
 347         int ret;
 348         char const *panel = getenv("panel");
 349         if (!panel) {
 350                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 351                         struct display_info_t const *dev = displays+i;
 352                         if (dev->detect && dev->detect(dev)) {
 353                                 panel = dev->mode.name;
 354                                 printf("auto-detected panel %s\n", panel);
 355                                 break;
 356                         }
 357                 }
 358                 if (!panel) {
 359                         panel = displays[0].mode.name;
 360                         printf("No panel detected: default to %s\n", panel);
 361                         i = 0;
 362                 }
 363         } else {
 364                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 365                         if (!strcmp(panel, displays[i].mode.name))
 366                                 break;
 367                 }
 368         }
 369         if (i < ARRAY_SIZE(displays)) {
 370                 ret = ipuv3_fb_init(&displays[i].mode, 0,
 371                                     displays[i].pixfmt);
 372                 if (!ret) {
 373                         displays[i].enable(displays+i);
 374                         printf("Display: %s (%ux%u)\n",
 375                                displays[i].mode.name,
 376                                displays[i].mode.xres,
 377                                displays[i].mode.yres);
 378                 } else
 379                         printf("LCD %s cannot be configured: %d\n",
 380                                displays[i].mode.name, ret);
 381         } else {
 382                 printf("unsupported panel %s\n", panel);
 383                 return -EINVAL;
 384         }
 385
 386         return 0;
 387 }
 388
 389 static void setup_display(void)
 390 {
 391         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 392         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 393         int reg;
 394
 395         /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
 396         imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
 397
 398         enable_ipu_clock();
 399         imx_setup_hdmi();
 400
 401         /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
 402         reg = readl(&mxc_ccm->CCGR3);
 403         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
 404         writel(reg, &mxc_ccm->CCGR3);
 405
 406         /* set LDB0, LDB1 clk select to 011/011 */
 407         reg = readl(&mxc_ccm->cs2cdr);
 408         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 409                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 410         reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 411               | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 412         writel(reg, &mxc_ccm->cs2cdr);
 413
 414         reg = readl(&mxc_ccm->cscmr2);
 415         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
 416         writel(reg, &mxc_ccm->cscmr2);
 417
 418         reg = readl(&mxc_ccm->chsccdr);
 419         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 420                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 421         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 422                 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
 423         writel(reg, &mxc_ccm->chsccdr);
 424
 425         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 426              | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
 427              | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 428              | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 429              | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 430              | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 431              | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 432              | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
 433              | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
 434         writel(reg, &iomux->gpr[2]);
 435
 436         reg = readl(&iomux->gpr[3]);
 437         reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
 438                         | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 439             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 440                << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
 441         writel(reg, &iomux->gpr[3]);
 442 }
 443 #endif /* CONFIG_VIDEO_IPUV3 */
 444
 445 /*
 446  * Do not overwrite the console
 447  * Use always serial for U-Boot console
 448  */
 449 int overwrite_console(void)
 450 {
 451         return 1;
 452 }
 453
 454 int board_eth_init(bd_t *bis)
 455 {
 456         setup_iomux_enet();
 457
 458         return cpu_eth_init(bis);
 459 }
 460
 461 int board_early_init_f(void)
 462 {
 463         setup_iomux_uart();
 464 #if defined(CONFIG_VIDEO_IPUV3)
 465         setup_display();
 466 #endif
 467
 468         return 0;
 469 }
 470
 471 int board_init(void)
 472 {
 473         /* address of boot parameters */
 474         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 475
 476 #ifdef CONFIG_MXC_SPI
 477         setup_spi();
 478 #endif
 479
 480         return 0;
 481 }
 482
 483 #ifdef CONFIG_CMD_BMODE
 484 static const struct boot_mode board_boot_modes[] = {
 485         /* 4 bit bus width */
 486         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 487         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 488         /* 8 bit bus width */
 489         {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 490         {NULL,   0},
 491 };
 492 #endif
 493
 494 int board_late_init(void)
 495 {
 496 #ifdef CONFIG_CMD_BMODE
 497         add_board_boot_modes(board_boot_modes);
 498 #endif
 499
 500         return 0;
 501 }
 502
 503 int checkboard(void)
 504 {
 505         puts("Board: MX6-SabreSD\n");
 506         return 0;
 507 }