2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/errno.h>
15 #include <asm/imx-common/iomux-v3.h>
16 #include <asm/imx-common/boot_mode.h>
18 #include <fsl_esdhc.h>
21 #include <asm/arch/mxc_hdmi.h>
22 #include <asm/arch/crm_regs.h>
24 #include <ipu_pixfmt.h>
26 #include <asm/arch/sys_proto.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
30 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
31 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
33 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
34 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
35 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
37 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
38 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
40 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
41 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
45 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
50 iomux_v3_cfg_t const uart1_pads[] = {
51 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
52 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
55 iomux_v3_cfg_t const enet_pads[] = {
56 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
57 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
58 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
59 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
60 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
61 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
62 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
63 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
64 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
65 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
66 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
67 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
68 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
69 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
70 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
71 /* AR8031 PHY Reset */
72 MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
75 static void setup_iomux_enet(void)
77 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
79 /* Reset AR8031 PHY */
80 gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
82 gpio_set_value(IMX_GPIO_NR(1, 25), 1);
85 iomux_v3_cfg_t const usdhc2_pads[] = {
86 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93 MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94 MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95 MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
99 iomux_v3_cfg_t const usdhc3_pads[] = {
100 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
101 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
102 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
103 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
104 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
110 MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
113 iomux_v3_cfg_t const usdhc4_pads[] = {
114 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
115 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
116 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
120 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
121 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
126 iomux_v3_cfg_t const ecspi1_pads[] = {
127 MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
128 MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
129 MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
130 MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
133 static void setup_spi(void)
135 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
138 iomux_v3_cfg_t const pcie_pads[] = {
139 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */
140 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */
143 static void setup_pcie(void)
145 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
148 iomux_v3_cfg_t const di0_pads[] = {
149 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */
150 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */
151 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */
154 static void setup_iomux_uart(void)
156 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
159 #ifdef CONFIG_FSL_ESDHC
160 struct fsl_esdhc_cfg usdhc_cfg[3] = {
166 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
167 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
169 int board_mmc_getcd(struct mmc *mmc)
171 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
174 switch (cfg->esdhc_base) {
175 case USDHC2_BASE_ADDR:
176 ret = !gpio_get_value(USDHC2_CD_GPIO);
178 case USDHC3_BASE_ADDR:
179 ret = !gpio_get_value(USDHC3_CD_GPIO);
181 case USDHC4_BASE_ADDR:
182 ret = 1; /* eMMC/uSDHC4 is always present */
189 int board_mmc_init(bd_t *bis)
195 * According to the board_mmc_init() the following map is done:
196 * (U-boot device node) (Physical Port)
201 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
204 imx_iomux_v3_setup_multiple_pads(
205 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
206 gpio_direction_input(USDHC2_CD_GPIO);
207 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
210 imx_iomux_v3_setup_multiple_pads(
211 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
212 gpio_direction_input(USDHC3_CD_GPIO);
213 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
216 imx_iomux_v3_setup_multiple_pads(
217 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
218 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
221 printf("Warning: you configured more USDHC controllers"
222 "(%d) then supported by the board (%d)\n",
223 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
227 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
234 int mx6_rgmii_rework(struct phy_device *phydev)
238 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
239 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
240 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
241 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
243 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
246 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
248 /* introduce tx clock delay */
249 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
250 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
252 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
257 int board_phy_config(struct phy_device *phydev)
259 mx6_rgmii_rework(phydev);
261 if (phydev->drv->config)
262 phydev->drv->config(phydev);
267 #if defined(CONFIG_VIDEO_IPUV3)
268 struct display_info_t {
272 int (*detect)(struct display_info_t const *dev);
273 void (*enable)(struct display_info_t const *dev);
274 struct fb_videomode mode;
277 static int detect_hdmi(struct display_info_t const *dev)
279 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
280 return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
284 static void disable_lvds(struct display_info_t const *dev)
286 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
288 int reg = readl(&iomux->gpr[2]);
290 reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
291 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
293 writel(reg, &iomux->gpr[2]);
296 static void do_enable_hdmi(struct display_info_t const *dev)
299 imx_enable_hdmi_phy();
302 static void enable_lvds(struct display_info_t const *dev)
304 struct iomuxc *iomux = (struct iomuxc *)
306 u32 reg = readl(&iomux->gpr[2]);
307 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
308 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
309 writel(reg, &iomux->gpr[2]);
312 static struct display_info_t const displays[] = {{
315 .pixfmt = IPU_PIX_FMT_RGB666,
317 .enable = enable_lvds,
319 .name = "Hannstar-XGA",
331 .vmode = FB_VMODE_NONINTERLACED
335 .pixfmt = IPU_PIX_FMT_RGB24,
336 .detect = detect_hdmi,
337 .enable = do_enable_hdmi,
351 .vmode = FB_VMODE_NONINTERLACED
354 int board_video_skip(void)
358 char const *panel = getenv("panel");
360 for (i = 0; i < ARRAY_SIZE(displays); i++) {
361 struct display_info_t const *dev = displays+i;
362 if (dev->detect && dev->detect(dev)) {
363 panel = dev->mode.name;
364 printf("auto-detected panel %s\n", panel);
369 panel = displays[0].mode.name;
370 printf("No panel detected: default to %s\n", panel);
374 for (i = 0; i < ARRAY_SIZE(displays); i++) {
375 if (!strcmp(panel, displays[i].mode.name))
379 if (i < ARRAY_SIZE(displays)) {
380 ret = ipuv3_fb_init(&displays[i].mode, 0,
383 displays[i].enable(displays+i);
384 printf("Display: %s (%ux%u)\n",
385 displays[i].mode.name,
386 displays[i].mode.xres,
387 displays[i].mode.yres);
389 printf("LCD %s cannot be configured: %d\n",
390 displays[i].mode.name, ret);
392 printf("unsupported panel %s\n", panel);
399 static void setup_display(void)
401 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
402 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
405 /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
406 imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
411 /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
412 reg = readl(&mxc_ccm->CCGR3);
413 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
414 writel(reg, &mxc_ccm->CCGR3);
416 /* set LDB0, LDB1 clk select to 011/011 */
417 reg = readl(&mxc_ccm->cs2cdr);
418 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
419 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
420 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
421 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
422 writel(reg, &mxc_ccm->cs2cdr);
424 reg = readl(&mxc_ccm->cscmr2);
425 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
426 writel(reg, &mxc_ccm->cscmr2);
428 reg = readl(&mxc_ccm->chsccdr);
429 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
430 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
431 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
432 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
433 writel(reg, &mxc_ccm->chsccdr);
435 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
436 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
437 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
438 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
439 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
440 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
441 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
442 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
443 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
444 writel(reg, &iomux->gpr[2]);
446 reg = readl(&iomux->gpr[3]);
447 reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
448 | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
449 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
450 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
451 writel(reg, &iomux->gpr[3]);
453 #endif /* CONFIG_VIDEO_IPUV3 */
456 * Do not overwrite the console
457 * Use always serial for U-Boot console
459 int overwrite_console(void)
464 int board_eth_init(bd_t *bis)
469 return cpu_eth_init(bis);
472 int board_early_init_f(void)
475 #if defined(CONFIG_VIDEO_IPUV3)
484 /* address of boot parameters */
485 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
487 #ifdef CONFIG_MXC_SPI
494 #ifdef CONFIG_CMD_BMODE
495 static const struct boot_mode board_boot_modes[] = {
496 /* 4 bit bus width */
497 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
498 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
499 /* 8 bit bus width */
500 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
505 int board_late_init(void)
507 #ifdef CONFIG_CMD_BMODE
508 add_board_boot_modes(board_boot_modes);
516 puts("Board: MX6-SabreSD\n");