git.sur5r.net Git - u-boot/blob - board/freescale/mx6sabresd/mx6sabresd.c

   1 /*
   2  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <asm/errno.h>
  14 #include <asm/gpio.h>
  15 #include <asm/imx-common/mxc_i2c.h>
  16 #include <asm/imx-common/iomux-v3.h>
  17 #include <asm/imx-common/boot_mode.h>
  18 #include <asm/imx-common/video.h>
  19 #include <mmc.h>
  20 #include <fsl_esdhc.h>
  21 #include <miiphy.h>
  22 #include <netdev.h>
  23 #include <asm/arch/mxc_hdmi.h>
  24 #include <asm/arch/crm_regs.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <i2c.h>
  28 #include <power/pmic.h>
  29 #include <power/pfuze100_pmic.h>
  30 #include "../common/pfuze.h"
  31 #include <asm/arch/mx6-ddr.h>
  32 #include <usb.h>
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  37         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  38         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  39
  40 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  41         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  42         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  43
  44 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  45         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  46
  47 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  48                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  49
  50 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  51         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  52         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  53
  54 #define I2C_PMIC        1
  55
  56 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  57
  58 #define DISP0_PWR_EN    IMX_GPIO_NR(1, 21)
  59
  60 int dram_init(void)
  61 {
  62         gd->ram_size = imx_ddr_size();
  63         return 0;
  64 }
  65
  66 static iomux_v3_cfg_t const uart1_pads[] = {
  67         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  68         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  69 };
  70
  71 static iomux_v3_cfg_t const enet_pads[] = {
  72         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  73         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
  74         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  75         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  76         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  77         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  78         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  79         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  80         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  81         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  82         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  83         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  84         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  85         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  86         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  87         /* AR8031 PHY Reset */
  88         MX6_PAD_ENET_CRS_DV__GPIO1_IO25         | MUX_PAD_CTRL(NO_PAD_CTRL),
  89 };
  90
  91 static void setup_iomux_enet(void)
  92 {
  93         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  94
  95         /* Reset AR8031 PHY */
  96         gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
  97         mdelay(10);
  98         gpio_set_value(IMX_GPIO_NR(1, 25), 1);
  99         udelay(100);
 100 }
 101
 102 static iomux_v3_cfg_t const usdhc2_pads[] = {
 103         MX6_PAD_SD2_CLK__SD2_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 104         MX6_PAD_SD2_CMD__SD2_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 105         MX6_PAD_SD2_DAT0__SD2_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 106         MX6_PAD_SD2_DAT1__SD2_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 107         MX6_PAD_SD2_DAT2__SD2_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 108         MX6_PAD_SD2_DAT3__SD2_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 109         MX6_PAD_NANDF_D4__SD2_DATA4     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 110         MX6_PAD_NANDF_D5__SD2_DATA5     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 111         MX6_PAD_NANDF_D6__SD2_DATA6     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 112         MX6_PAD_NANDF_D7__SD2_DATA7     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 113         MX6_PAD_NANDF_D2__GPIO2_IO02    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 114 };
 115
 116 static iomux_v3_cfg_t const usdhc3_pads[] = {
 117         MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 118         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 119         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 120         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 121         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 122         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 123         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 124         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 125         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 126         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 127         MX6_PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 128 };
 129
 130 static iomux_v3_cfg_t const usdhc4_pads[] = {
 131         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 135         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 136         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 137         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 138         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 139         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 140         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 141 };
 142
 143 static iomux_v3_cfg_t const ecspi1_pads[] = {
 144         MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 145         MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 146         MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 147         MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
 148 };
 149
 150 static iomux_v3_cfg_t const rgb_pads[] = {
 151         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
 152         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 153         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL),
 154         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL),
 155         MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL),
 156         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 157         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
 158         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
 159         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
 160         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
 161         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 162         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
 163         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
 164         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL),
 165         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL),
 166         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 167         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 168         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 169         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL),
 170         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL),
 171         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 172         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL),
 173         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL),
 174         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 175         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL),
 176         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL),
 177         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 178         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 179         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),
 180         MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 181 };
 182
 183 static void enable_rgb(struct display_info_t const *dev)
 184 {
 185         imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));
 186         gpio_direction_output(DISP0_PWR_EN, 1);
 187 }
 188
 189 static struct i2c_pads_info i2c_pad_info1 = {
 190         .scl = {
 191                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 192                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 193                 .gp = IMX_GPIO_NR(4, 12)
 194         },
 195         .sda = {
 196                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 197                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 198                 .gp = IMX_GPIO_NR(4, 13)
 199         }
 200 };
 201
 202 static void setup_spi(void)
 203 {
 204         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 205 }
 206
 207 iomux_v3_cfg_t const pcie_pads[] = {
 208         MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),        /* POWER */
 209         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),        /* RESET */
 210 };
 211
 212 static void setup_pcie(void)
 213 {
 214         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
 215 }
 216
 217 iomux_v3_cfg_t const di0_pads[] = {
 218         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,        /* DISP0_CLK */
 219         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,               /* DISP0_HSYNC */
 220         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,               /* DISP0_VSYNC */
 221 };
 222
 223 static void setup_iomux_uart(void)
 224 {
 225         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 226 }
 227
 228 #ifdef CONFIG_FSL_ESDHC
 229 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 230         {USDHC2_BASE_ADDR},
 231         {USDHC3_BASE_ADDR},
 232         {USDHC4_BASE_ADDR},
 233 };
 234
 235 #define USDHC2_CD_GPIO  IMX_GPIO_NR(2, 2)
 236 #define USDHC3_CD_GPIO  IMX_GPIO_NR(2, 0)
 237
 238 int board_mmc_get_env_dev(int devno)
 239 {
 240         return devno - 1;
 241 }
 242
 243 int board_mmc_getcd(struct mmc *mmc)
 244 {
 245         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 246         int ret = 0;
 247
 248         switch (cfg->esdhc_base) {
 249         case USDHC2_BASE_ADDR:
 250                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 251                 break;
 252         case USDHC3_BASE_ADDR:
 253                 ret = !gpio_get_value(USDHC3_CD_GPIO);
 254                 break;
 255         case USDHC4_BASE_ADDR:
 256                 ret = 1; /* eMMC/uSDHC4 is always present */
 257                 break;
 258         }
 259
 260         return ret;
 261 }
 262
 263 int board_mmc_init(bd_t *bis)
 264 {
 265 #ifndef CONFIG_SPL_BUILD
 266         int ret;
 267         int i;
 268
 269         /*
 270          * According to the board_mmc_init() the following map is done:
 271          * (U-Boot device node)    (Physical Port)
 272          * mmc0                    SD2
 273          * mmc1                    SD3
 274          * mmc2                    eMMC
 275          */
 276         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 277                 switch (i) {
 278                 case 0:
 279                         imx_iomux_v3_setup_multiple_pads(
 280                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 281                         gpio_direction_input(USDHC2_CD_GPIO);
 282                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 283                         break;
 284                 case 1:
 285                         imx_iomux_v3_setup_multiple_pads(
 286                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 287                         gpio_direction_input(USDHC3_CD_GPIO);
 288                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 289                         break;
 290                 case 2:
 291                         imx_iomux_v3_setup_multiple_pads(
 292                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 293                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 294                         break;
 295                 default:
 296                         printf("Warning: you configured more USDHC controllers"
 297                                "(%d) then supported by the board (%d)\n",
 298                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 299                         return -EINVAL;
 300                 }
 301
 302                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 303                 if (ret)
 304                         return ret;
 305         }
 306
 307         return 0;
 308 #else
 309         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 310         unsigned reg = readl(&psrc->sbmr1) >> 11;
 311         /*
 312          * Upon reading BOOT_CFG register the following map is done:
 313          * Bit 11 and 12 of BOOT_CFG register can determine the current
 314          * mmc port
 315          * 0x1                  SD1
 316          * 0x2                  SD2
 317          * 0x3                  SD4
 318          */
 319
 320         switch (reg & 0x3) {
 321         case 0x1:
 322                 imx_iomux_v3_setup_multiple_pads(
 323                         usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 324                 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 325                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 326                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 327                 break;
 328         case 0x2:
 329                 imx_iomux_v3_setup_multiple_pads(
 330                         usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 331                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 332                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 333                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 334                 break;
 335         case 0x3:
 336                 imx_iomux_v3_setup_multiple_pads(
 337                         usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 338                 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
 339                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 340                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 341                 break;
 342         }
 343
 344         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 345 #endif
 346 }
 347 #endif
 348
 349 #if defined(CONFIG_VIDEO_IPUV3)
 350 static void disable_lvds(struct display_info_t const *dev)
 351 {
 352         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 353
 354         int reg = readl(&iomux->gpr[2]);
 355
 356         reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
 357                  IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
 358
 359         writel(reg, &iomux->gpr[2]);
 360 }
 361
 362 static void do_enable_hdmi(struct display_info_t const *dev)
 363 {
 364         disable_lvds(dev);
 365         imx_enable_hdmi_phy();
 366 }
 367
 368 struct display_info_t const displays[] = {{
 369         .bus    = -1,
 370         .addr   = 0,
 371         .pixfmt = IPU_PIX_FMT_RGB666,
 372         .detect = NULL,
 373         .enable = NULL,
 374         .mode   = {
 375                 .name           = "Hannstar-XGA",
 376                 .refresh        = 60,
 377                 .xres           = 1024,
 378                 .yres           = 768,
 379                 .pixclock       = 15384,
 380                 .left_margin    = 160,
 381                 .right_margin   = 24,
 382                 .upper_margin   = 29,
 383                 .lower_margin   = 3,
 384                 .hsync_len      = 136,
 385                 .vsync_len      = 6,
 386                 .sync           = FB_SYNC_EXT,
 387                 .vmode          = FB_VMODE_NONINTERLACED
 388 } }, {
 389         .bus    = -1,
 390         .addr   = 0,
 391         .pixfmt = IPU_PIX_FMT_RGB24,
 392         .detect = detect_hdmi,
 393         .enable = do_enable_hdmi,
 394         .mode   = {
 395                 .name           = "HDMI",
 396                 .refresh        = 60,
 397                 .xres           = 1024,
 398                 .yres           = 768,
 399                 .pixclock       = 15384,
 400                 .left_margin    = 160,
 401                 .right_margin   = 24,
 402                 .upper_margin   = 29,
 403                 .lower_margin   = 3,
 404                 .hsync_len      = 136,
 405                 .vsync_len      = 6,
 406                 .sync           = FB_SYNC_EXT,
 407                 .vmode          = FB_VMODE_NONINTERLACED
 408 } }, {
 409         .bus    = 0,
 410         .addr   = 0,
 411         .pixfmt = IPU_PIX_FMT_RGB24,
 412         .detect = NULL,
 413         .enable = enable_rgb,
 414         .mode   = {
 415                 .name           = "SEIKO-WVGA",
 416                 .refresh        = 60,
 417                 .xres           = 800,
 418                 .yres           = 480,
 419                 .pixclock       = 29850,
 420                 .left_margin    = 89,
 421                 .right_margin   = 164,
 422                 .upper_margin   = 23,
 423                 .lower_margin   = 10,
 424                 .hsync_len      = 10,
 425                 .vsync_len      = 10,
 426                 .sync           = 0,
 427                 .vmode          = FB_VMODE_NONINTERLACED
 428 } } };
 429 size_t display_count = ARRAY_SIZE(displays);
 430
 431 static void setup_display(void)
 432 {
 433         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 434         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 435         int reg;
 436
 437         /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
 438         imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
 439
 440         enable_ipu_clock();
 441         imx_setup_hdmi();
 442
 443         /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
 444         reg = readl(&mxc_ccm->CCGR3);
 445         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
 446         writel(reg, &mxc_ccm->CCGR3);
 447
 448         /* set LDB0, LDB1 clk select to 011/011 */
 449         reg = readl(&mxc_ccm->cs2cdr);
 450         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 451                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 452         reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 453               | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 454         writel(reg, &mxc_ccm->cs2cdr);
 455
 456         reg = readl(&mxc_ccm->cscmr2);
 457         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
 458         writel(reg, &mxc_ccm->cscmr2);
 459
 460         reg = readl(&mxc_ccm->chsccdr);
 461         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 462                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 463         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 464                 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
 465         writel(reg, &mxc_ccm->chsccdr);
 466
 467         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 468              | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
 469              | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 470              | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 471              | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 472              | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 473              | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 474              | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
 475              | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
 476         writel(reg, &iomux->gpr[2]);
 477
 478         reg = readl(&iomux->gpr[3]);
 479         reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
 480                         | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 481             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 482                << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
 483         writel(reg, &iomux->gpr[3]);
 484 }
 485 #endif /* CONFIG_VIDEO_IPUV3 */
 486
 487 /*
 488  * Do not overwrite the console
 489  * Use always serial for U-Boot console
 490  */
 491 int overwrite_console(void)
 492 {
 493         return 1;
 494 }
 495
 496 int board_eth_init(bd_t *bis)
 497 {
 498         setup_iomux_enet();
 499         setup_pcie();
 500
 501         return cpu_eth_init(bis);
 502 }
 503
 504 #ifdef CONFIG_USB_EHCI_MX6
 505 #define USB_OTHERREGS_OFFSET    0x800
 506 #define UCTRL_PWR_POL           (1 << 9)
 507
 508 static iomux_v3_cfg_t const usb_otg_pads[] = {
 509         MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 510         MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
 511 };
 512
 513 static iomux_v3_cfg_t const usb_hc1_pads[] = {
 514         MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 515 };
 516
 517 static void setup_usb(void)
 518 {
 519         imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 520                                          ARRAY_SIZE(usb_otg_pads));
 521
 522         /*
 523          * set daisy chain for otg_pin_id on 6q.
 524          * for 6dl, this bit is reserved
 525          */
 526         imx_iomux_set_gpr_register(1, 13, 1, 0);
 527
 528         imx_iomux_v3_setup_multiple_pads(usb_hc1_pads,
 529                                          ARRAY_SIZE(usb_hc1_pads));
 530 }
 531
 532 int board_ehci_hcd_init(int port)
 533 {
 534         u32 *usbnc_usb_ctrl;
 535
 536         if (port > 1)
 537                 return -EINVAL;
 538
 539         usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
 540                                  port * 4);
 541
 542         setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
 543
 544         return 0;
 545 }
 546
 547 int board_ehci_power(int port, int on)
 548 {
 549         switch (port) {
 550         case 0:
 551                 break;
 552         case 1:
 553                 if (on)
 554                         gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
 555                 else
 556                         gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
 557                 break;
 558         default:
 559                 printf("MXC USB port %d not yet supported\n", port);
 560                 return -EINVAL;
 561         }
 562
 563         return 0;
 564 }
 565 #endif
 566
 567 int board_early_init_f(void)
 568 {
 569         setup_iomux_uart();
 570 #if defined(CONFIG_VIDEO_IPUV3)
 571         setup_display();
 572 #endif
 573
 574         return 0;
 575 }
 576
 577 int board_init(void)
 578 {
 579         /* address of boot parameters */
 580         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 581
 582 #ifdef CONFIG_MXC_SPI
 583         setup_spi();
 584 #endif
 585         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 586
 587 #ifdef CONFIG_USB_EHCI_MX6
 588         setup_usb();
 589 #endif
 590
 591         return 0;
 592 }
 593
 594 int power_init_board(void)
 595 {
 596         struct pmic *p;
 597         unsigned int reg;
 598         int ret;
 599
 600         p = pfuze_common_init(I2C_PMIC);
 601         if (!p)
 602                 return -ENODEV;
 603
 604         ret = pfuze_mode_init(p, APS_PFM);
 605         if (ret < 0)
 606                 return ret;
 607
 608         /* Increase VGEN3 from 2.5 to 2.8V */
 609         pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
 610         reg &= ~LDO_VOL_MASK;
 611         reg |= LDOB_2_80V;
 612         pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
 613
 614         /* Increase VGEN5 from 2.8 to 3V */
 615         pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
 616         reg &= ~LDO_VOL_MASK;
 617         reg |= LDOB_3_00V;
 618         pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
 619
 620         return 0;
 621 }
 622
 623 #ifdef CONFIG_MXC_SPI
 624 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 625 {
 626         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
 627 }
 628 #endif
 629
 630 #ifdef CONFIG_CMD_BMODE
 631 static const struct boot_mode board_boot_modes[] = {
 632         /* 4 bit bus width */
 633         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 634         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 635         /* 8 bit bus width */
 636         {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
 637         {NULL,   0},
 638 };
 639 #endif
 640
 641 int board_late_init(void)
 642 {
 643 #ifdef CONFIG_CMD_BMODE
 644         add_board_boot_modes(board_boot_modes);
 645 #endif
 646
 647 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 648         setenv("board_name", "SABRESD");
 649
 650         if (is_mx6dqp())
 651                 setenv("board_rev", "MX6QP");
 652         else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
 653                 setenv("board_rev", "MX6Q");
 654         else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
 655                 setenv("board_rev", "MX6DL");
 656 #endif
 657
 658         return 0;
 659 }
 660
 661 int checkboard(void)
 662 {
 663         puts("Board: MX6-SabreSD\n");
 664         return 0;
 665 }
 666
 667 #ifdef CONFIG_SPL_BUILD
 668 #include <spl.h>
 669 #include <libfdt.h>
 670
 671 const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
 672         .dram_sdclk_0 =  0x00020030,
 673         .dram_sdclk_1 =  0x00020030,
 674         .dram_cas =  0x00020030,
 675         .dram_ras =  0x00020030,
 676         .dram_reset =  0x00020030,
 677         .dram_sdcke0 =  0x00003000,
 678         .dram_sdcke1 =  0x00003000,
 679         .dram_sdba2 =  0x00000000,
 680         .dram_sdodt0 =  0x00003030,
 681         .dram_sdodt1 =  0x00003030,
 682         .dram_sdqs0 =  0x00000030,
 683         .dram_sdqs1 =  0x00000030,
 684         .dram_sdqs2 =  0x00000030,
 685         .dram_sdqs3 =  0x00000030,
 686         .dram_sdqs4 =  0x00000030,
 687         .dram_sdqs5 =  0x00000030,
 688         .dram_sdqs6 =  0x00000030,
 689         .dram_sdqs7 =  0x00000030,
 690         .dram_dqm0 =  0x00020030,
 691         .dram_dqm1 =  0x00020030,
 692         .dram_dqm2 =  0x00020030,
 693         .dram_dqm3 =  0x00020030,
 694         .dram_dqm4 =  0x00020030,
 695         .dram_dqm5 =  0x00020030,
 696         .dram_dqm6 =  0x00020030,
 697         .dram_dqm7 =  0x00020030,
 698 };
 699
 700 const struct mx6dq_iomux_ddr_regs mx6dqp_ddr_ioregs = {
 701         .dram_sdclk_0 =  0x00000030,
 702         .dram_sdclk_1 =  0x00000030,
 703         .dram_cas =  0x00000030,
 704         .dram_ras =  0x00000030,
 705         .dram_reset =  0x00000030,
 706         .dram_sdcke0 =  0x00003000,
 707         .dram_sdcke1 =  0x00003000,
 708         .dram_sdba2 =  0x00000000,
 709         .dram_sdodt0 =  0x00003030,
 710         .dram_sdodt1 =  0x00003030,
 711         .dram_sdqs0 =  0x00000030,
 712         .dram_sdqs1 =  0x00000030,
 713         .dram_sdqs2 =  0x00000030,
 714         .dram_sdqs3 =  0x00000030,
 715         .dram_sdqs4 =  0x00000030,
 716         .dram_sdqs5 =  0x00000030,
 717         .dram_sdqs6 =  0x00000030,
 718         .dram_sdqs7 =  0x00000030,
 719         .dram_dqm0 =  0x00000030,
 720         .dram_dqm1 =  0x00000030,
 721         .dram_dqm2 =  0x00000030,
 722         .dram_dqm3 =  0x00000030,
 723         .dram_dqm4 =  0x00000030,
 724         .dram_dqm5 =  0x00000030,
 725         .dram_dqm6 =  0x00000030,
 726         .dram_dqm7 =  0x00000030,
 727 };
 728
 729 const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
 730         .grp_ddr_type =  0x000C0000,
 731         .grp_ddrmode_ctl =  0x00020000,
 732         .grp_ddrpke =  0x00000000,
 733         .grp_addds =  0x00000030,
 734         .grp_ctlds =  0x00000030,
 735         .grp_ddrmode =  0x00020000,
 736         .grp_b0ds =  0x00000030,
 737         .grp_b1ds =  0x00000030,
 738         .grp_b2ds =  0x00000030,
 739         .grp_b3ds =  0x00000030,
 740         .grp_b4ds =  0x00000030,
 741         .grp_b5ds =  0x00000030,
 742         .grp_b6ds =  0x00000030,
 743         .grp_b7ds =  0x00000030,
 744 };
 745
 746 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
 747         .p0_mpwldectrl0 =  0x001F001F,
 748         .p0_mpwldectrl1 =  0x001F001F,
 749         .p1_mpwldectrl0 =  0x00440044,
 750         .p1_mpwldectrl1 =  0x00440044,
 751         .p0_mpdgctrl0 =  0x434B0350,
 752         .p0_mpdgctrl1 =  0x034C0359,
 753         .p1_mpdgctrl0 =  0x434B0350,
 754         .p1_mpdgctrl1 =  0x03650348,
 755         .p0_mprddlctl =  0x4436383B,
 756         .p1_mprddlctl =  0x39393341,
 757         .p0_mpwrdlctl =  0x35373933,
 758         .p1_mpwrdlctl =  0x48254A36,
 759 };
 760
 761 const struct mx6_mmdc_calibration mx6dqp_mmcd_calib = {
 762         .p0_mpwldectrl0 =  0x001B001E,
 763         .p0_mpwldectrl1 =  0x002E0029,
 764         .p1_mpwldectrl0 =  0x001B002A,
 765         .p1_mpwldectrl1 =  0x0019002C,
 766         .p0_mpdgctrl0 =  0x43240334,
 767         .p0_mpdgctrl1 =  0x0324031A,
 768         .p1_mpdgctrl0 =  0x43340344,
 769         .p1_mpdgctrl1 =  0x03280276,
 770         .p0_mprddlctl =  0x44383A3E,
 771         .p1_mprddlctl =  0x3C3C3846,
 772         .p0_mpwrdlctl =  0x2E303230,
 773         .p1_mpwrdlctl =  0x38283E34,
 774 };
 775
 776 /* MT41K128M16JT-125 */
 777 static struct mx6_ddr3_cfg mem_ddr = {
 778         .mem_speed = 1600,
 779         .density = 2,
 780         .width = 16,
 781         .banks = 8,
 782         .rowaddr = 14,
 783         .coladdr = 10,
 784         .pagesz = 2,
 785         .trcd = 1375,
 786         .trcmin = 4875,
 787         .trasmin = 3500,
 788 };
 789
 790 static void ccgr_init(void)
 791 {
 792         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 793
 794         writel(0x00C03F3F, &ccm->CCGR0);
 795         writel(0x0030FC03, &ccm->CCGR1);
 796         writel(0x0FFFC000, &ccm->CCGR2);
 797         writel(0x3FF00000, &ccm->CCGR3);
 798         writel(0x00FFF300, &ccm->CCGR4);
 799         writel(0x0F0000C3, &ccm->CCGR5);
 800         writel(0x000003FF, &ccm->CCGR6);
 801 }
 802
 803 static void gpr_init(void)
 804 {
 805         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 806
 807         /* enable AXI cache for VDOA/VPU/IPU */
 808         writel(0xF00000CF, &iomux->gpr[4]);
 809         if (is_mx6dqp()) {
 810                 /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
 811                 writel(0x007F007F, &iomux->gpr[6]);
 812                 writel(0x007F007F, &iomux->gpr[7]);
 813         } else {
 814                 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 815                 writel(0x007F007F, &iomux->gpr[6]);
 816                 writel(0x007F007F, &iomux->gpr[7]);
 817         }
 818 }
 819
 820 /*
 821  * This section requires the differentiation between iMX6 Sabre boards, but
 822  * for now, it will configure only for the mx6q variant.
 823  */
 824 static void spl_dram_init(void)
 825 {
 826         struct mx6_ddr_sysinfo sysinfo = {
 827                 /* width of data bus:0=16,1=32,2=64 */
 828                 .dsize = 2,
 829                 /* config for full 4GB range so that get_mem_size() works */
 830                 .cs_density = 32, /* 32Gb per CS */
 831                 /* single chip select */
 832                 .ncs = 1,
 833                 .cs1_mirror = 0,
 834                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 835                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 836                 .walat = 1,     /* Write additional latency */
 837                 .ralat = 5,     /* Read additional latency */
 838                 .mif3_mode = 3, /* Command prediction working mode */
 839                 .bi_on = 1,     /* Bank interleaving enabled */
 840                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 841                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 842                 .ddr_type = DDR_TYPE_DDR3,
 843         };
 844
 845         if (is_mx6dqp()) {
 846                 mx6dq_dram_iocfg(64, &mx6dqp_ddr_ioregs, &mx6_grp_ioregs);
 847                 mx6_dram_cfg(&sysinfo, &mx6dqp_mmcd_calib, &mem_ddr);
 848         } else {
 849                 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 850                 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
 851         }
 852 }
 853
 854 void board_init_f(ulong dummy)
 855 {
 856         /* setup AIPS and disable watchdog */
 857         arch_cpu_init();
 858
 859         ccgr_init();
 860         gpr_init();
 861
 862         /* iomux and setup of i2c */
 863         board_early_init_f();
 864
 865         /* setup GP timer */
 866         timer_init();
 867
 868         /* UART clocks enabled and gd valid - init serial console */
 869         preloader_console_init();
 870
 871         /* DDR initialization */
 872         spl_dram_init();
 873
 874         /* Clear the BSS. */
 875         memset(__bss_start, 0, __bss_end - __bss_start);
 876
 877         /* load/boot image from boot device */
 878         board_init_r(NULL, 0);
 879 }
 880 #endif