1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
5 * Author: Ye Li <ye.li@nxp.com>
8 #include <asm/arch/clock.h>
9 #include <asm/arch/crm_regs.h>
10 #include <asm/arch/iomux.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/sys_proto.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/mach-imx/boot_mode.h>
18 #include <linux/sizes.h>
20 #include <fsl_esdhc.h>
23 #include <power/pmic.h>
24 #include <power/pfuze100_pmic.h>
25 #include "../common/pfuze.h"
27 #include <usb/ehci-ci.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
33 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
34 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
36 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
37 PAD_CTL_SPEED_HIGH | \
38 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
40 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
41 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
43 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
44 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
46 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
47 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
49 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
53 gd->ram_size = imx_ddr_size();
58 static iomux_v3_cfg_t const uart1_pads[] = {
59 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
60 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
63 static iomux_v3_cfg_t const fec2_pads[] = {
64 MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
65 MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
66 MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
67 MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
68 MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
69 MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
70 MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
71 MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
72 MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
73 MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
74 MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
75 MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
76 MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
77 MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
80 static void setup_iomux_uart(void)
82 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
85 static int setup_fec(void)
87 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
89 /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */
90 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
92 return enable_fec_anatop_clock(1, ENET_125MHZ);
95 int board_eth_init(bd_t *bis)
99 imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
102 ret = fecmxc_initialize_multi(bis, 1,
103 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
105 printf("FEC%d MXC: %s:failed\n", 1, __func__);
110 int board_phy_config(struct phy_device *phydev)
113 * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
114 * Phy control debug reg 0
116 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
117 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
119 /* rgmii tx clock delay enable */
120 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
121 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
123 if (phydev->drv->config)
124 phydev->drv->config(phydev);
129 int power_init_board(void)
133 u32 dev_id, rev_id, i;
135 u32 offset = PFUZE100_SW1CMODE;
137 ret = pmic_get("pfuze100", &dev);
144 dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
145 rev_id = pmic_reg_read(dev, PFUZE100_REVID);
146 printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
149 /* Init mode to APS_PFM */
150 pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
152 for (i = 0; i < switch_num - 1; i++)
153 pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
155 /* set SW1AB staby volatage 0.975V */
156 pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
158 /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
159 pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
161 /* set SW1C staby volatage 1.10V */
162 pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20);
164 /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
165 pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
170 #ifdef CONFIG_USB_EHCI_MX6
171 #define USB_OTHERREGS_OFFSET 0x800
172 #define UCTRL_PWR_POL (1 << 9)
174 static iomux_v3_cfg_t const usb_otg_pads[] = {
176 MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
177 MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
179 MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
182 static void setup_usb(void)
184 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
185 ARRAY_SIZE(usb_otg_pads));
188 int board_usb_phy_mode(int port)
191 return USB_INIT_HOST;
193 return usb_phy_mode(port);
196 int board_ehci_hcd_init(int port)
203 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
206 /* Set Power polarity */
207 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
213 int board_early_init_f(void)
220 #ifdef CONFIG_FSL_QSPI
222 #define QSPI_PAD_CTRL1 \
223 (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
224 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
226 static iomux_v3_cfg_t const quadspi_pads[] = {
227 MX6_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
228 MX6_PAD_QSPI1A_SCLK__QSPI1_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
229 MX6_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
230 MX6_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
231 MX6_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
232 MX6_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
233 MX6_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
234 MX6_PAD_QSPI1B_SCLK__QSPI1_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
235 MX6_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
236 MX6_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
237 MX6_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
238 MX6_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
241 int board_qspi_init(void)
244 imx_iomux_v3_setup_multiple_pads(quadspi_pads,
245 ARRAY_SIZE(quadspi_pads));
254 #ifdef CONFIG_NAND_MXS
255 iomux_v3_cfg_t gpmi_pads[] = {
256 MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
257 MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
258 MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
259 MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
260 MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
261 MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
262 MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
263 MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
264 MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
265 MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
266 MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
267 MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
268 MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
269 MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
270 MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
273 static void setup_gpmi_nand(void)
275 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
277 /* config gpmi nand iomux */
278 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
280 setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) |
281 MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) |
282 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3)));
284 /* enable apbh clock gating */
285 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
291 struct gpio_desc desc;
294 /* Address of boot parameters */
295 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
297 ret = dm_gpio_lookup_name("gpio@30_4", &desc);
301 ret = dm_gpio_request(&desc, "cpu_per_rst_b");
304 /* Reset CPU_PER_RST_B signal for enet phy and PCIE */
305 dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
307 dm_gpio_set_value(&desc, 1);
309 ret = dm_gpio_lookup_name("gpio@32_2", &desc);
313 ret = dm_gpio_request(&desc, "steer_enet");
317 dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
319 /* Set steering signal to L for selecting B0 */
320 dm_gpio_set_value(&desc, 0);
322 #ifdef CONFIG_USB_EHCI_MX6
326 #ifdef CONFIG_FSL_QSPI
330 #ifdef CONFIG_NAND_MXS
337 #ifdef CONFIG_CMD_BMODE
338 static const struct boot_mode board_boot_modes[] = {
339 {"sda", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)},
340 {"sdb", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
341 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
342 {"nand", MAKE_CFGVAL(0x82, 0x00, 0x00, 0x00)},
347 int board_late_init(void)
349 #ifdef CONFIG_CMD_BMODE
350 add_board_boot_modes(board_boot_modes);
358 puts("Board: MX6SX SABRE AUTO\n");