git.sur5r.net Git - u-boot/blob - board/freescale/mx7dsabresd/mx7dsabresd.c

   1 /*
   2  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <asm/arch/clock.h>
   8 #include <asm/arch/imx-regs.h>
   9 #include <asm/arch/mx7-pins.h>
  10 #include <asm/arch/sys_proto.h>
  11 #include <asm/gpio.h>
  12 #include <asm/imx-common/iomux-v3.h>
  13 #include <asm/io.h>
  14 #include <linux/sizes.h>
  15 #include <common.h>
  16 #include <fsl_esdhc.h>
  17 #include <mmc.h>
  18 #include <miiphy.h>
  19 #include <netdev.h>
  20 #include <power/pmic.h>
  21 #include <power/pfuze3000_pmic.h>
  22 #include "../common/pfuze.h"
  23 #include <i2c.h>
  24 #include <asm/imx-common/mxc_i2c.h>
  25 #include <asm/arch/crm_regs.h>
  26 #include <usb/ehci-fsl.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
  31         PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  32
  33 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  34         PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
  35
  36 #define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  37 #define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_3P3V_32OHM)
  38
  39 #define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  40
  41 #define I2C_PAD_CTRL    (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  42         PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
  43
  44 #ifdef CONFIG_SYS_I2C_MXC
  45 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  46 /* I2C1 for PMIC */
  47 static struct i2c_pads_info i2c_pad_info1 = {
  48         .scl = {
  49                 .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
  50                 .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
  51                 .gp = IMX_GPIO_NR(4, 8),
  52         },
  53         .sda = {
  54                 .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
  55                 .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
  56                 .gp = IMX_GPIO_NR(4, 9),
  57         },
  58 };
  59 #endif
  60
  61 int dram_init(void)
  62 {
  63         gd->ram_size = PHYS_SDRAM_SIZE;
  64
  65         return 0;
  66 }
  67
  68 static iomux_v3_cfg_t const wdog_pads[] = {
  69         MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  70 };
  71
  72 static iomux_v3_cfg_t const uart1_pads[] = {
  73         MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  74         MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  75 };
  76
  77 static iomux_v3_cfg_t const usdhc1_pads[] = {
  78         MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79         MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  80         MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  81         MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  82         MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  83         MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84
  85         MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86         MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87 };
  88
  89 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
  90         MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  91         MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  92         MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  93         MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  94         MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  95         MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96         MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97         MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98         MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99         MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 100         MX7D_PAD_SD3_STROBE__SD3_STROBE  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 101
 102         MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 103 };
 104
 105 #define IOX_SDI IMX_GPIO_NR(1, 9)
 106 #define IOX_STCP IMX_GPIO_NR(1, 12)
 107 #define IOX_SHCP IMX_GPIO_NR(1, 13)
 108
 109 static iomux_v3_cfg_t const iox_pads[] = {
 110         /* IOX_SDI */
 111         MX7D_PAD_GPIO1_IO09__GPIO1_IO9  | MUX_PAD_CTRL(NO_PAD_CTRL),
 112         /* IOX_STCP */
 113         MX7D_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 114         /* IOX_SHCP */
 115         MX7D_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
 116 };
 117
 118 /*
 119  * PCIE_DIS_B --> Q0
 120  * PCIE_RST_B --> Q1
 121  * HDMI_RST_B --> Q2
 122  * PERI_RST_B --> Q3
 123  * SENSOR_RST_B --> Q4
 124  * ENET_RST_B --> Q5
 125  * PERI_3V3_EN --> Q6
 126  * LCD_PWR_EN --> Q7
 127  */
 128 enum qn {
 129         PCIE_DIS_B,
 130         PCIE_RST_B,
 131         HDMI_RST_B,
 132         PERI_RST_B,
 133         SENSOR_RST_B,
 134         ENET_RST_B,
 135         PERI_3V3_EN,
 136         LCD_PWR_EN,
 137 };
 138
 139 enum qn_func {
 140         qn_reset,
 141         qn_enable,
 142         qn_disable,
 143 };
 144
 145 enum qn_level {
 146         qn_low = 0,
 147         qn_high = 1,
 148 };
 149
 150 static enum qn_level seq[3][2] = {
 151         {0, 1}, {1, 1}, {0, 0}
 152 };
 153
 154 static enum qn_func qn_output[8] = {
 155         qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable,
 156         qn_enable
 157 };
 158
 159 static void iox74lv_init(void)
 160 {
 161         int i;
 162
 163         for (i = 7; i >= 0; i--) {
 164                 gpio_direction_output(IOX_SHCP, 0);
 165                 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
 166                 udelay(500);
 167                 gpio_direction_output(IOX_SHCP, 1);
 168                 udelay(500);
 169         }
 170
 171         gpio_direction_output(IOX_STCP, 0);
 172         udelay(500);
 173         /*
 174           * shift register will be output to pins
 175           */
 176         gpio_direction_output(IOX_STCP, 1);
 177
 178         for (i = 7; i >= 0; i--) {
 179                 gpio_direction_output(IOX_SHCP, 0);
 180                 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
 181                 udelay(500);
 182                 gpio_direction_output(IOX_SHCP, 1);
 183                 udelay(500);
 184         }
 185         gpio_direction_output(IOX_STCP, 0);
 186         udelay(500);
 187         /*
 188           * shift register will be output to pins
 189           */
 190         gpio_direction_output(IOX_STCP, 1);
 191 };
 192
 193 #ifdef CONFIG_FEC_MXC
 194 static iomux_v3_cfg_t const fec1_pads[] = {
 195         MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 196         MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 197         MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 198         MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 199         MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 200         MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 201         MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
 202         MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 203         MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 204         MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 205         MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 206         MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 207         MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 208         MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 209 };
 210
 211 static void setup_iomux_fec(void)
 212 {
 213         imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
 214 }
 215 #endif
 216
 217 static void setup_iomux_uart(void)
 218 {
 219         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 220 }
 221
 222 #ifdef CONFIG_FSL_ESDHC
 223
 224 #define USDHC1_CD_GPIO  IMX_GPIO_NR(5, 0)
 225 #define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2)
 226 #define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11)
 227
 228 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 229         {USDHC1_BASE_ADDR, 0, 4},
 230         {USDHC3_BASE_ADDR},
 231 };
 232
 233 static int mmc_get_env_devno(void)
 234 {
 235         struct bootrom_sw_info **p =
 236                 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
 237
 238         u8 boot_type = (*p)->boot_dev_type;
 239         u8 dev_no = (*p)->boot_dev_instance;
 240
 241         /* If not boot from sd/mmc, use default value */
 242         if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
 243                 return CONFIG_SYS_MMC_ENV_DEV;
 244
 245         if (dev_no == 2)
 246                 dev_no--;
 247
 248         return dev_no;
 249 }
 250
 251 static int mmc_map_to_kernel_blk(int dev_no)
 252 {
 253         if (dev_no == 1)
 254                 dev_no++;
 255
 256         return dev_no;
 257 }
 258
 259 int board_mmc_getcd(struct mmc *mmc)
 260 {
 261         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 262         int ret = 0;
 263
 264         switch (cfg->esdhc_base) {
 265         case USDHC1_BASE_ADDR:
 266                 ret = !gpio_get_value(USDHC1_CD_GPIO);
 267                 break;
 268         case USDHC3_BASE_ADDR:
 269                 ret = 1; /* Assume uSDHC3 emmc is always present */
 270                 break;
 271         }
 272
 273         return ret;
 274 }
 275
 276 int board_mmc_init(bd_t *bis)
 277 {
 278         int i, ret;
 279         /*
 280          * According to the board_mmc_init() the following map is done:
 281          * (U-boot device node)    (Physical Port)
 282          * mmc0                    USDHC1
 283          * mmc2                    USDHC3 (eMMC)
 284          */
 285         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 286                 switch (i) {
 287                 case 0:
 288                         imx_iomux_v3_setup_multiple_pads(
 289                                 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 290                         gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
 291                         gpio_direction_input(USDHC1_CD_GPIO);
 292                         gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");
 293                         gpio_direction_output(USDHC1_PWR_GPIO, 0);
 294                         udelay(500);
 295                         gpio_direction_output(USDHC1_PWR_GPIO, 1);
 296                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 297                         break;
 298                 case 1:
 299                         imx_iomux_v3_setup_multiple_pads(
 300                                 usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));
 301                         gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr");
 302                         gpio_direction_output(USDHC3_PWR_GPIO, 0);
 303                         udelay(500);
 304                         gpio_direction_output(USDHC3_PWR_GPIO, 1);
 305                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 306                         break;
 307                 default:
 308                         printf("Warning: you configured more USDHC controllers"
 309                                 "(%d) than supported by the board\n", i + 1);
 310                         return -EINVAL;
 311                         }
 312
 313                         ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 314                         if (ret)
 315                                 return ret;
 316         }
 317
 318         return 0;
 319 }
 320
 321 static int check_mmc_autodetect(void)
 322 {
 323         char *autodetect_str = getenv("mmcautodetect");
 324
 325         if ((autodetect_str != NULL) &&
 326                 (strcmp(autodetect_str, "yes") == 0)) {
 327                 return 1;
 328         }
 329
 330         return 0;
 331 }
 332
 333 static void mmc_late_init(void)
 334 {
 335         char cmd[32];
 336         char mmcblk[32];
 337         u32 dev_no = mmc_get_env_devno();
 338
 339         if (!check_mmc_autodetect())
 340                 return;
 341
 342         setenv_ulong("mmcdev", dev_no);
 343
 344         /* Set mmcblk env */
 345         sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
 346                 mmc_map_to_kernel_blk(dev_no));
 347         setenv("mmcroot", mmcblk);
 348
 349         sprintf(cmd, "mmc dev %d", dev_no);
 350         run_command(cmd, 0);
 351 }
 352
 353 #endif
 354
 355 #ifdef CONFIG_FEC_MXC
 356 int board_eth_init(bd_t *bis)
 357 {
 358         int ret;
 359
 360         setup_iomux_fec();
 361
 362         ret = fecmxc_initialize_multi(bis, 0,
 363                 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
 364         if (ret)
 365                 printf("FEC1 MXC: %s:failed\n", __func__);
 366
 367         return ret;
 368 }
 369
 370 static int setup_fec(void)
 371 {
 372         struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
 373                 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
 374
 375         /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
 376         clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
 377                 (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
 378                  IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
 379
 380         return set_clk_enet(ENET_125MHz);
 381 }
 382
 383
 384 int board_phy_config(struct phy_device *phydev)
 385 {
 386         /* enable rgmii rxc skew and phy mode select to RGMII copper */
 387         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21);
 388         phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8);
 389         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f);
 390         phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);
 391
 392         if (phydev->drv->config)
 393                 phydev->drv->config(phydev);
 394         return 0;
 395 }
 396 #endif
 397
 398 int board_early_init_f(void)
 399 {
 400         setup_iomux_uart();
 401
 402         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 403
 404         return 0;
 405 }
 406
 407 int board_init(void)
 408 {
 409         /* address of boot parameters */
 410         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 411
 412         imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
 413
 414         iox74lv_init();
 415
 416 #ifdef CONFIG_FEC_MXC
 417         setup_fec();
 418 #endif
 419
 420         return 0;
 421 }
 422
 423 #ifdef CONFIG_POWER
 424 #define I2C_PMIC        0
 425 int power_init_board(void)
 426 {
 427         struct pmic *p;
 428         int ret;
 429         unsigned int reg, rev_id;
 430
 431         ret = power_pfuze3000_init(I2C_PMIC);
 432         if (ret)
 433                 return ret;
 434
 435         p = pmic_get("PFUZE3000");
 436         ret = pmic_probe(p);
 437         if (ret)
 438                 return ret;
 439
 440         pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
 441         pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
 442         printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
 443
 444         /* disable Low Power Mode during standby mode */
 445         pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
 446         reg |= 0x1;
 447         pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
 448
 449         return 0;
 450 }
 451 #endif
 452
 453 int board_late_init(void)
 454 {
 455         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
 456
 457 #ifdef CONFIG_ENV_IS_IN_MMC
 458         mmc_late_init();
 459 #endif
 460
 461         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
 462
 463         set_wdog_reset(wdog);
 464
 465         /*
 466          * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
 467          * since we use PMIC_PWRON to reset the board.
 468          */
 469         clrsetbits_le16(&wdog->wcr, 0, 0x10);
 470
 471         return 0;
 472 }
 473
 474 int checkboard(void)
 475 {
 476         puts("Board: i.MX7D SABRESD\n");
 477
 478         return 0;
 479 }
 480
 481 #ifdef CONFIG_USB_EHCI_MX7
 482 static iomux_v3_cfg_t const usb_otg1_pads[] = {
 483         MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 484 };
 485
 486 static iomux_v3_cfg_t const usb_otg2_pads[] = {
 487         MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 488 };
 489
 490 int board_ehci_hcd_init(int port)
 491 {
 492         switch (port) {
 493         case 0:
 494                 imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
 495                                                  ARRAY_SIZE(usb_otg1_pads));
 496                 break;
 497         case 1:
 498                 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
 499                                                  ARRAY_SIZE(usb_otg2_pads));
 500                 break;
 501         default:
 502                 printf("MXC USB port %d not yet supported\n", port);
 503                 return -EINVAL;
 504         }
 505         return 0;
 506 }
 507 #endif