3 The P1010RDB is a Freescale reference design board that hosts the P1010 SoC.
5 The P1010 is a cost-effective, low-power, highly integrated host processor
6 based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz),
7 that addresses the requirements of several routing, gateways, storage, consumer,
8 and industrial applications. Applications of interest include the main CPUs and
9 I/O processors in network attached storage (NAS), the voice over IP (VoIP)
10 router/gateway, and wireless LAN (WLAN) and industrial controllers.
12 The P1010RDB board features are as follows:
14 - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
15 - 32 Mbyte NOR flash single-chip memory
16 - 32 Mbyte NAND flash memory
17 - 256 Kbit M24256 I2C EEPROM
19 - I2C Board EEPROM 128x8 bit memory
20 - SD/MMC connector to interface with the SD memory card
23 - Lane0: x1 mini-PCIe slot
24 - Lane1: x1 PCIe standard slot
26 - 1 internal SATA connector to 2.5” 160G SATA2 HDD
27 - 1 eSATA connector to rear panel
28 - 10/100/1000 BaseT Ethernet ports:
29 - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO
30 - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221
31 - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221
33 - x1 USB2.0 port via an external ULPI PHY to micro-AB connector
34 - x1 USB2.0 port via an internal UTMI PHY to micro-AB connector
36 - 2 DB-9 female connectors for FlexCAN bus(revision 2.0B)
39 - DUART interface: supports two UARTs up to 115200 bps for
41 - RJ45 connectors are used for these 2 UART ports.
43 - 2 FXS ports connected via an external SLIC to the TDM interface.
44 SLIC is controllled via SPI.
45 - 1 FXO port connected via a relay to FXS for switchover to POTS
47 - Mini-ITX power supply connector
48 - JTAG/COP for debugging
49 IEEE Std. 1588 signals for test and measurement
50 Real-time clock on I2C bus
52 - support critical POR setting changed via switch on board
54 - 6-layer routing (4-layer signals, 2-layer power and ground)
57 Physical Memory Map on P1010RDB
58 ===============================
59 Address Start Address End Memory type Attributes
60 0x0000_0000 0x3fff_ffff DDR 1G Cacheable
61 0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
62 0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable
63 0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
64 0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable
65 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
66 0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0
67 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
70 Serial Port Configuration on P1010RDB
71 =====================================
72 Configure the serial port of the attached computer with the following values:
73 -Data rate: 115200 bps
74 -Number of data bits: 8
76 -Number of Stop bits: 1
77 -Flow Control: Hardware/None
80 Settings of DIP-switch
81 ======================
82 SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash
83 SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash
84 SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash
85 Note: 1 stands for 'on', 0 stands for 'off'
90 If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
91 "fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example:
92 setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
93 By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
94 is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM
95 instead of to CAN/UART1.
98 Build and burn U-Boot to NOR flash
99 ==================================
100 1. Build u-boot.bin image
102 export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
105 2. Burn u-boot.bin into NOR flash
106 => tftp $loadaddr $uboot
107 => protect off eff40000 +$filesize
108 => erase eff40000 +$filesize
109 => cp.b $loadaddr eff40000 $filesize
111 3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on.
116 1. Burn u-boot.bin into alternate NOR bank
117 => tftp $loadaddr $uboot
118 => protect off eef40000 +$filesize
119 => erase eef40000 +$filesize
120 => cp.b $loadaddr eef40000 $filesize
122 2. Switch to alternate NOR bank
127 SW1[8]= OFF: Upper bank used for booting start
128 SW1[8]= ON: Lower bank used for booting start
129 CPLD NOR bank selection register address 0xFFB00009 Bit[0]:
130 0 - boot from upper 4 sectors
131 1 - boot from lower 4 sectors
134 Build and burn U-Boot to NAND flash
135 ===================================
136 1. Build u-boot.bin image
138 export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
141 2. Burn u-boot-nand.bin into NAND flash
142 => tftp $loadaddr $uboot-nand
143 => nand erase 0 $filesize
144 => nand write $loadaddr 0 $filesize
146 3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
149 Build and burn U-Boot to SPI flash
150 ==================================
151 1. Build u-boot-spi.bin image
152 make P1010RDB_SPIFLASH_config; make
153 Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb
154 Download u-boot.bin to linux and you can find some config files
155 under /usr/share such as config_xx.dat. Do below command:
156 boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \
158 to generate u-boot-spi.bin.
160 2. Burn u-boot-spi.bin into SPI flash
161 => tftp $loadaddr $uboot-spi
163 => sf write $loadaddr 0 $filesize
165 3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
168 CPLD POR setting registers
169 ==========================
170 1. Set POR switch selection register (addr 0xFFB00011) to 0.
171 2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with
173 If change boot ROM location to NOR or NAND flash, need write the IFC_CS0
174 switch command by I2C.
175 3. Send reset command.
176 After reset, the new POR setting will be implemented.
178 Two examples are given in below:
179 Switch from NOR to NAND boot with default frequency:
186 Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
198 Boot Linux from network using TFTP on P1010RDB
199 ==============================================
200 Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
201 => tftp 1000000 uImage
202 => tftp 2000000 p1010rdb.dtb
203 => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
204 => bootm 1000000 3000000 2000000
207 For more details, please refer to P1010RDB User Guide and access website