2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/processor.h>
10 #include <asm/cache.h>
11 #include <asm/immap_85xx.h>
15 #include <fdt_support.h>
21 #include <asm/fsl_serdes.h>
23 #include <asm/fsl_pci.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 #define GPIO4_PCIE_RESET_SET 0x08000000
30 #define MUX_CPLD_CAN_UART 0x00
31 #define MUX_CPLD_TDM 0x01
32 #define MUX_CPLD_SPICS0_FLASH 0x00
33 #define MUX_CPLD_SPICS0_SLIC 0x02
34 #define PMUXCR1_IFC_MASK 0x00ffff00
35 #define PMUXCR1_SDHC_MASK 0x00fff000
36 #define PMUXCR1_SDHC_ENABLE 0x00555000
53 static uint sd_ifc_mux;
56 u8 cpld_ver; /* cpld revision */
57 #if defined(CONFIG_P1010RDB_PA)
58 u8 pcba_ver; /* pcb revision number */
61 u8 bank_sel; /* NOR Flash bank */
67 u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
68 u8 por0; /* POR Options */
69 u8 por1; /* POR Options */
70 u8 por2; /* POR Options */
71 u8 por3; /* POR Options */
72 #elif defined(CONFIG_P1010RDB_PB)
77 int board_early_init_f(void)
79 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
80 struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
82 /* Clock configuration to access CPLD using IFC(GPCM) */
83 setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
85 * Reset PCIe slots via GPIO4
87 setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
88 setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
93 int board_early_init_r(void)
95 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
96 int flash_esel = find_tlb_idx((void *)flashbase, 1);
99 * Remap Boot flash region to caching-inhibited
100 * so that flash can be erased properly.
103 /* Flush d-cache and invalidate i-cache of any FLASH data */
107 if (flash_esel == -1) {
108 /* very unlikely unless something is messed up */
109 puts("Error: Could not find TLB for FLASH BASE\n");
110 flash_esel = 2; /* give our best effort to continue */
112 /* invalidate existing TLB entry for flash */
113 disable_tlb(flash_esel);
116 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
117 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
118 0, flash_esel, BOOKE_PAGESZ_16M, 1);
120 set_tlb(1, flashbase + 0x1000000,
121 CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
122 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
123 0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
128 void pci_init_board(void)
130 fsl_pcie_init_board(0);
132 #endif /* ifdef CONFIG_PCI */
134 int config_board_mux(int ctrl_type)
136 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
139 #if defined(CONFIG_P1010RDB_PA)
140 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
144 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
146 i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
148 i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
149 sd_ifc_mux = MUX_TYPE_IFC;
150 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
153 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
155 i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
157 i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
158 sd_ifc_mux = MUX_TYPE_SDHC;
159 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
160 PMUXCR1_SDHC_ENABLE);
162 case MUX_TYPE_SPIFLASH:
163 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
166 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
167 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
170 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
175 #elif defined(CONFIG_P1010RDB_PB)
176 uint orig_bus = i2c_get_bus_num();
177 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
181 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
182 clrbits_8(&tmp, 0x04);
183 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
184 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
185 clrbits_8(&tmp, 0x04);
186 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
187 sd_ifc_mux = MUX_TYPE_IFC;
188 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
191 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
192 setbits_8(&tmp, 0x04);
193 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
194 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
195 clrbits_8(&tmp, 0x04);
196 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
197 sd_ifc_mux = MUX_TYPE_SDHC;
198 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
199 PMUXCR1_SDHC_ENABLE);
201 case MUX_TYPE_SPIFLASH:
202 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
203 clrbits_8(&tmp, 0x80);
204 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
205 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
206 clrbits_8(&tmp, 0x80);
207 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
210 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
211 setbits_8(&tmp, 0x82);
212 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
213 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
214 clrbits_8(&tmp, 0x82);
215 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
218 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
219 clrbits_8(&tmp, 0x02);
220 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
221 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
222 clrbits_8(&tmp, 0x02);
223 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
225 case MUX_TYPE_CS0_NOR:
226 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
227 clrbits_8(&tmp, 0x08);
228 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
229 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
230 clrbits_8(&tmp, 0x08);
231 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
233 case MUX_TYPE_CS0_NAND:
234 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
235 setbits_8(&tmp, 0x08);
236 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
237 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
238 clrbits_8(&tmp, 0x08);
239 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
244 i2c_set_bus_num(orig_bus);
249 #ifdef CONFIG_P1010RDB_PB
250 int i2c_pca9557_read(int type)
254 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
255 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
259 val = (val & 0x10) >> 4;
261 case I2C_READ_PCB_VER:
262 val = ((val & 0x60) >> 5) + 1;
274 struct cpu_type *cpu;
275 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
279 #if defined(CONFIG_P1010RDB_PA)
280 printf("Board: %sRDB-PA, ", cpu->name);
281 #elif defined(CONFIG_P1010RDB_PB)
282 printf("Board: %sRDB-PB, ", cpu->name);
283 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
284 i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
285 val = 0x0; /* no polarity inversion */
286 i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
290 /* switch to IFC to read info from CPLD */
291 config_board_mux(MUX_TYPE_IFC);
294 #if defined(CONFIG_P1010RDB_PA)
295 val = (in_8(&cpld_data->pcba_ver) & 0xf);
296 printf("PCB: v%x.0\n", val);
297 #elif defined(CONFIG_P1010RDB_PB)
298 val = in_8(&cpld_data->cpld_ver);
299 printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
300 printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
301 val = in_8(&cpld_data->rom_loc) & 0xf;
305 config_board_mux(MUX_TYPE_CS0_NOR);
306 printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
310 val = 0x60; /* set pca9557 pin input/output */
311 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
314 config_board_mux(MUX_TYPE_IFC);
315 config_board_mux(MUX_TYPE_CS0_NAND);
319 config_board_mux(MUX_TYPE_IFC);
330 #ifdef CONFIG_TSEC_ENET
331 int board_eth_init(bd_t *bis)
333 struct fsl_pq_mdio_info mdio_info;
334 struct tsec_info_struct tsec_info[4];
335 struct cpu_type *cpu;
341 SET_STD_TSEC_INFO(tsec_info[num], 1);
345 SET_STD_TSEC_INFO(tsec_info[num], 2);
349 /* P1014 and it's derivatives do not support eTSEC3 */
350 if (cpu->soc_ver != SVR_P1014) {
351 SET_STD_TSEC_INFO(tsec_info[num], 3);
356 printf("No TSECs initialized\n");
360 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
361 mdio_info.name = DEFAULT_MII_NAME;
363 fsl_pq_mdio_init(bis, &mdio_info);
365 tsec_eth_init(bis, tsec_info, num);
367 return pci_eth_init(bis);
371 #if defined(CONFIG_OF_BOARD_SETUP)
372 void fdt_del_flexcan(void *blob)
376 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
377 "fsl,p1010-flexcan")) >= 0) {
378 fdt_del_node(blob, nodeoff);
382 void fdt_del_spi_flash(void *blob)
386 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
387 "spansion,s25sl12801")) >= 0) {
388 fdt_del_node(blob, nodeoff);
392 void fdt_del_spi_slic(void *blob)
396 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
397 "zarlink,le88266")) >= 0) {
398 fdt_del_node(blob, nodeoff);
402 void fdt_del_tdm(void *blob)
406 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
407 "fsl,starlite-tdm")) >= 0) {
408 fdt_del_node(blob, nodeoff);
412 void fdt_del_sdhc(void *blob)
416 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
417 "fsl,esdhc")) >= 0) {
418 fdt_del_node(blob, nodeoff);
422 void fdt_del_ifc(void *blob)
426 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
428 fdt_del_node(blob, nodeoff);
432 void fdt_disable_uart1(void *blob)
436 nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
437 CONFIG_SYS_NS16550_COM2);
440 fdt_status_disabled(blob, nodeoff);
442 printf("WARNING unable to set status for fsl,ns16550 "
443 "uart1: %s\n", fdt_strerror(nodeoff));
447 int ft_board_setup(void *blob, bd_t *bd)
451 struct cpu_type *cpu;
455 ft_cpu_setup(blob, bd);
457 base = getenv_bootm_low();
458 size = getenv_bootm_size();
460 #if defined(CONFIG_PCI)
464 fdt_fixup_memory(blob, (u64)base, (u64)size);
466 #if defined(CONFIG_HAS_FSL_DR_USB)
467 fdt_fixup_dr_usb(blob, bd);
470 /* P1014 and it's derivatives don't support CAN and eTSEC3 */
471 if (cpu->soc_ver == SVR_P1014) {
472 fdt_del_flexcan(blob);
473 fdt_del_node_and_alias(blob, "ethernet2");
476 /* Delete IFC node as IFC pins are multiplexing with SDHC */
477 if (sd_ifc_mux != MUX_TYPE_IFC)
482 if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
484 fdt_del_spi_slic(blob);
485 } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
486 fdt_del_flexcan(blob);
487 fdt_del_spi_flash(blob);
488 fdt_disable_uart1(blob);
491 * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
492 * explicitly, defaultly spi_cs_sel to spi-flash instead of
496 fdt_del_flexcan(blob);
497 fdt_disable_uart1(blob);
505 int board_mmc_init(bd_t *bis)
507 config_board_mux(MUX_TYPE_SDHC);
511 void board_reset(void)
513 /* mux to IFC to enable CPLD for reset */
514 if (sd_ifc_mux != MUX_TYPE_IFC)
515 config_board_mux(MUX_TYPE_IFC);
520 int misc_init_r(void)
522 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
524 if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
525 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
526 MPC85xx_PMUXCR_CAN1_UART |
527 MPC85xx_PMUXCR_CAN2_TDM |
528 MPC85xx_PMUXCR_CAN2_UART);
529 config_board_mux(MUX_TYPE_CAN);
530 } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
531 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
532 MPC85xx_PMUXCR_CAN1_UART);
533 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
534 MPC85xx_PMUXCR_CAN1_TDM);
535 clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
536 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
537 config_board_mux(MUX_TYPE_TDM);
539 /* defaultly spi_cs_sel to flash */
540 config_board_mux(MUX_TYPE_SPIFLASH);
543 if (hwconfig("esdhc"))
544 config_board_mux(MUX_TYPE_SDHC);
545 else if (hwconfig("ifc"))
546 config_board_mux(MUX_TYPE_IFC);
548 #ifdef CONFIG_P1010RDB_PB
549 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
554 static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
558 return CMD_RET_USAGE;
559 if (strcmp(argv[1], "ifc") == 0)
560 config_board_mux(MUX_TYPE_IFC);
561 else if (strcmp(argv[1], "sdhc") == 0)
562 config_board_mux(MUX_TYPE_SDHC);
564 return CMD_RET_USAGE;
569 mux, 2, 0, pin_mux_cmd,
570 "configure multiplexing pin for IFC/SDHC bus in runtime",
571 "bus_type (e.g. mux sdhc)"