2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/processor.h>
10 #include <asm/cache.h>
11 #include <asm/immap_85xx.h>
15 #include <fdt_support.h>
21 #include <asm/fsl_serdes.h>
23 #include <asm/fsl_pci.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 #define GPIO4_PCIE_RESET_SET 0x08000000
30 #define MUX_CPLD_CAN_UART 0x00
31 #define MUX_CPLD_TDM 0x01
32 #define MUX_CPLD_SPICS0_FLASH 0x00
33 #define MUX_CPLD_SPICS0_SLIC 0x02
34 #define PMUXCR1_IFC_MASK 0x00ffff00
35 #define PMUXCR1_SDHC_MASK 0x00fff000
36 #define PMUXCR1_SDHC_ENABLE 0x00555000
53 static uint sd_ifc_mux;
56 u8 cpld_ver; /* cpld revision */
57 #if defined(CONFIG_P1010RDB_PA)
58 u8 pcba_ver; /* pcb revision number */
61 u8 bank_sel; /* NOR Flash bank */
67 u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
68 u8 por0; /* POR Options */
69 u8 por1; /* POR Options */
70 u8 por2; /* POR Options */
71 u8 por3; /* POR Options */
72 #elif defined(CONFIG_P1010RDB_PB)
77 int board_early_init_f(void)
79 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
80 struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
82 /* Clock configuration to access CPLD using IFC(GPCM) */
83 setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
85 * Reset PCIe slots via GPIO4
87 setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
88 setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
93 int board_early_init_r(void)
95 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
96 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
99 * Remap Boot flash region to caching-inhibited
100 * so that flash can be erased properly.
103 /* Flush d-cache and invalidate i-cache of any FLASH data */
107 /* invalidate existing TLB entry for flash */
108 disable_tlb(flash_esel);
110 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
111 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
112 0, flash_esel, BOOKE_PAGESZ_16M, 1);
114 set_tlb(1, flashbase + 0x1000000,
115 CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
116 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
117 0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
122 void pci_init_board(void)
124 fsl_pcie_init_board(0);
126 #endif /* ifdef CONFIG_PCI */
128 int config_board_mux(int ctrl_type)
130 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
133 #if defined(CONFIG_P1010RDB_PA)
134 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
138 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
140 i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
142 i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
143 sd_ifc_mux = MUX_TYPE_IFC;
144 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
147 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
149 i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
151 i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
152 sd_ifc_mux = MUX_TYPE_SDHC;
153 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
154 PMUXCR1_SDHC_ENABLE);
156 case MUX_TYPE_SPIFLASH:
157 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
160 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
161 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
164 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
169 #elif defined(CONFIG_P1010RDB_PB)
170 uint orig_bus = i2c_get_bus_num();
171 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
175 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
176 clrbits_8(&tmp, 0x04);
177 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
178 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
179 clrbits_8(&tmp, 0x04);
180 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
181 sd_ifc_mux = MUX_TYPE_IFC;
182 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
185 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
186 setbits_8(&tmp, 0x04);
187 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
188 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
189 clrbits_8(&tmp, 0x04);
190 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
191 sd_ifc_mux = MUX_TYPE_SDHC;
192 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
193 PMUXCR1_SDHC_ENABLE);
195 case MUX_TYPE_SPIFLASH:
196 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
197 clrbits_8(&tmp, 0x80);
198 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
199 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
200 clrbits_8(&tmp, 0x80);
201 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
204 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
205 setbits_8(&tmp, 0x82);
206 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
207 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
208 clrbits_8(&tmp, 0x82);
209 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
212 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
213 clrbits_8(&tmp, 0x02);
214 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
215 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
216 clrbits_8(&tmp, 0x02);
217 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
219 case MUX_TYPE_CS0_NOR:
220 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
221 clrbits_8(&tmp, 0x08);
222 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
223 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
224 clrbits_8(&tmp, 0x08);
225 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
227 case MUX_TYPE_CS0_NAND:
228 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
229 setbits_8(&tmp, 0x08);
230 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
231 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
232 clrbits_8(&tmp, 0x08);
233 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
238 i2c_set_bus_num(orig_bus);
243 #ifdef CONFIG_P1010RDB_PB
244 int i2c_pca9557_read(int type)
248 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
249 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
253 val = (val & 0x10) >> 4;
255 case I2C_READ_PCB_VER:
256 val = ((val & 0x60) >> 5) + 1;
268 struct cpu_type *cpu;
269 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
273 #if defined(CONFIG_P1010RDB_PA)
274 printf("Board: %sRDB-PA, ", cpu->name);
275 #elif defined(CONFIG_P1010RDB_PB)
276 printf("Board: %sRDB-PB, ", cpu->name);
277 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
278 i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
279 val = 0x0; /* no polarity inversion */
280 i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
284 /* switch to IFC to read info from CPLD */
285 config_board_mux(MUX_TYPE_IFC);
288 #if defined(CONFIG_P1010RDB_PA)
289 val = (in_8(&cpld_data->pcba_ver) & 0xf);
290 printf("PCB: v%x.0\n", val);
291 #elif defined(CONFIG_P1010RDB_PB)
292 val = in_8(&cpld_data->cpld_ver);
293 printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
294 printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
295 val = in_8(&cpld_data->rom_loc) & 0xf;
299 config_board_mux(MUX_TYPE_CS0_NOR);
300 printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
304 val = 0x60; /* set pca9557 pin input/output */
305 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
308 config_board_mux(MUX_TYPE_IFC);
309 config_board_mux(MUX_TYPE_CS0_NAND);
313 config_board_mux(MUX_TYPE_IFC);
324 #ifdef CONFIG_TSEC_ENET
325 int board_eth_init(bd_t *bis)
327 struct fsl_pq_mdio_info mdio_info;
328 struct tsec_info_struct tsec_info[4];
329 struct cpu_type *cpu;
335 SET_STD_TSEC_INFO(tsec_info[num], 1);
339 SET_STD_TSEC_INFO(tsec_info[num], 2);
343 /* P1014 and it's derivatives do not support eTSEC3 */
344 if (cpu->soc_ver != SVR_P1014) {
345 SET_STD_TSEC_INFO(tsec_info[num], 3);
350 printf("No TSECs initialized\n");
354 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
355 mdio_info.name = DEFAULT_MII_NAME;
357 fsl_pq_mdio_init(bis, &mdio_info);
359 tsec_eth_init(bis, tsec_info, num);
361 return pci_eth_init(bis);
365 #if defined(CONFIG_OF_BOARD_SETUP)
366 void fdt_del_flexcan(void *blob)
370 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
371 "fsl,p1010-flexcan")) >= 0) {
372 fdt_del_node(blob, nodeoff);
376 void fdt_del_spi_flash(void *blob)
380 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
381 "spansion,s25sl12801")) >= 0) {
382 fdt_del_node(blob, nodeoff);
386 void fdt_del_spi_slic(void *blob)
390 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
391 "zarlink,le88266")) >= 0) {
392 fdt_del_node(blob, nodeoff);
396 void fdt_del_tdm(void *blob)
400 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
401 "fsl,starlite-tdm")) >= 0) {
402 fdt_del_node(blob, nodeoff);
406 void fdt_del_sdhc(void *blob)
410 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
411 "fsl,esdhc")) >= 0) {
412 fdt_del_node(blob, nodeoff);
416 void fdt_del_ifc(void *blob)
420 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
422 fdt_del_node(blob, nodeoff);
426 void fdt_disable_uart1(void *blob)
430 nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
431 CONFIG_SYS_NS16550_COM2);
434 fdt_status_disabled(blob, nodeoff);
436 printf("WARNING unable to set status for fsl,ns16550 "
437 "uart1: %s\n", fdt_strerror(nodeoff));
441 void ft_board_setup(void *blob, bd_t *bd)
445 struct cpu_type *cpu;
449 ft_cpu_setup(blob, bd);
451 base = getenv_bootm_low();
452 size = getenv_bootm_size();
454 #if defined(CONFIG_PCI)
458 fdt_fixup_memory(blob, (u64)base, (u64)size);
460 #if defined(CONFIG_HAS_FSL_DR_USB)
461 fdt_fixup_dr_usb(blob, bd);
464 /* P1014 and it's derivatives don't support CAN and eTSEC3 */
465 if (cpu->soc_ver == SVR_P1014) {
466 fdt_del_flexcan(blob);
467 fdt_del_node_and_alias(blob, "ethernet2");
470 /* Delete IFC node as IFC pins are multiplexing with SDHC */
471 if (sd_ifc_mux != MUX_TYPE_IFC)
476 if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
478 fdt_del_spi_slic(blob);
479 } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
480 fdt_del_flexcan(blob);
481 fdt_del_spi_flash(blob);
482 fdt_disable_uart1(blob);
485 * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
486 * explicitly, defaultly spi_cs_sel to spi-flash instead of
490 fdt_del_flexcan(blob);
491 fdt_disable_uart1(blob);
497 int board_mmc_init(bd_t *bis)
499 config_board_mux(MUX_TYPE_SDHC);
503 void board_reset(void)
505 /* mux to IFC to enable CPLD for reset */
506 if (sd_ifc_mux != MUX_TYPE_IFC)
507 config_board_mux(MUX_TYPE_IFC);
512 int misc_init_r(void)
514 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
516 if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
517 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
518 MPC85xx_PMUXCR_CAN1_UART |
519 MPC85xx_PMUXCR_CAN2_TDM |
520 MPC85xx_PMUXCR_CAN2_UART);
521 config_board_mux(MUX_TYPE_CAN);
522 } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
523 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
524 MPC85xx_PMUXCR_CAN1_UART);
525 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
526 MPC85xx_PMUXCR_CAN1_TDM);
527 clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
528 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
529 config_board_mux(MUX_TYPE_TDM);
531 /* defaultly spi_cs_sel to flash */
532 config_board_mux(MUX_TYPE_SPIFLASH);
535 if (hwconfig("esdhc"))
536 config_board_mux(MUX_TYPE_SDHC);
537 else if (hwconfig("ifc"))
538 config_board_mux(MUX_TYPE_IFC);
540 #ifdef CONFIG_P1010RDB_PB
541 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
546 static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
550 return CMD_RET_USAGE;
551 if (strcmp(argv[1], "ifc") == 0)
552 config_board_mux(MUX_TYPE_IFC);
553 else if (strcmp(argv[1], "sdhc") == 0)
554 config_board_mux(MUX_TYPE_SDHC);
556 return CMD_RET_USAGE;
561 mux, 2, 0, pin_mux_cmd,
562 "configure multiplexing pin for IFC/SDHC bus in runtime",
563 "bus_type (e.g. mux sdhc)"