2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/processor.h>
10 #include <asm/cache.h>
11 #include <asm/immap_85xx.h>
15 #include <fdt_support.h>
21 #include <asm/fsl_serdes.h>
23 #include <asm/fsl_pci.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 #define GPIO4_PCIE_RESET_SET 0x08000000
30 #define MUX_CPLD_CAN_UART 0x00
31 #define MUX_CPLD_TDM 0x01
32 #define MUX_CPLD_SPICS0_FLASH 0x00
33 #define MUX_CPLD_SPICS0_SLIC 0x02
34 #define PMUXCR1_IFC_MASK 0x00ffff00
35 #define PMUXCR1_SDHC_MASK 0x00fff000
36 #define PMUXCR1_SDHC_ENABLE 0x00555000
53 static uint sd_ifc_mux;
56 u8 cpld_ver; /* cpld revision */
57 #if defined(CONFIG_TARGET_P1010RDB_PA)
58 u8 pcba_ver; /* pcb revision number */
61 u8 bank_sel; /* NOR Flash bank */
67 u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
68 u8 por0; /* POR Options */
69 u8 por1; /* POR Options */
70 u8 por2; /* POR Options */
71 u8 por3; /* POR Options */
72 #elif defined(CONFIG_TARGET_P1010RDB_PB)
77 int board_early_init_f(void)
79 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
80 struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
81 /* Clock configuration to access CPLD using IFC(GPCM) */
82 setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
84 * Reset PCIe slots via GPIO4
86 setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
87 setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
92 int board_early_init_r(void)
94 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
95 int flash_esel = find_tlb_idx((void *)flashbase, 1);
98 * Remap Boot flash region to caching-inhibited
99 * so that flash can be erased properly.
102 /* Flush d-cache and invalidate i-cache of any FLASH data */
106 if (flash_esel == -1) {
107 /* very unlikely unless something is messed up */
108 puts("Error: Could not find TLB for FLASH BASE\n");
109 flash_esel = 2; /* give our best effort to continue */
111 /* invalidate existing TLB entry for flash */
112 disable_tlb(flash_esel);
115 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
116 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
117 0, flash_esel, BOOKE_PAGESZ_16M, 1);
119 set_tlb(1, flashbase + 0x1000000,
120 CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
121 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
122 0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
127 void pci_init_board(void)
129 fsl_pcie_init_board(0);
131 #endif /* ifdef CONFIG_PCI */
133 int config_board_mux(int ctrl_type)
135 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
138 #if defined(CONFIG_TARGET_P1010RDB_PA)
139 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
143 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
145 i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
147 i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
148 sd_ifc_mux = MUX_TYPE_IFC;
149 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
152 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
154 i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
156 i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
157 sd_ifc_mux = MUX_TYPE_SDHC;
158 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
159 PMUXCR1_SDHC_ENABLE);
161 case MUX_TYPE_SPIFLASH:
162 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
165 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
166 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
169 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
174 #elif defined(CONFIG_TARGET_P1010RDB_PB)
175 uint orig_bus = i2c_get_bus_num();
176 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
180 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
181 clrbits_8(&tmp, 0x04);
182 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
183 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
184 clrbits_8(&tmp, 0x04);
185 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
186 sd_ifc_mux = MUX_TYPE_IFC;
187 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
190 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
191 setbits_8(&tmp, 0x04);
192 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
193 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
194 clrbits_8(&tmp, 0x04);
195 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
196 sd_ifc_mux = MUX_TYPE_SDHC;
197 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
198 PMUXCR1_SDHC_ENABLE);
200 case MUX_TYPE_SPIFLASH:
201 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
202 clrbits_8(&tmp, 0x80);
203 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
204 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
205 clrbits_8(&tmp, 0x80);
206 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
209 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
210 setbits_8(&tmp, 0x82);
211 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
212 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
213 clrbits_8(&tmp, 0x82);
214 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
217 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
218 clrbits_8(&tmp, 0x02);
219 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
220 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
221 clrbits_8(&tmp, 0x02);
222 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
224 case MUX_TYPE_CS0_NOR:
225 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
226 clrbits_8(&tmp, 0x08);
227 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
228 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
229 clrbits_8(&tmp, 0x08);
230 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
232 case MUX_TYPE_CS0_NAND:
233 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
234 setbits_8(&tmp, 0x08);
235 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
236 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
237 clrbits_8(&tmp, 0x08);
238 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
243 i2c_set_bus_num(orig_bus);
248 #ifdef CONFIG_TARGET_P1010RDB_PB
249 int i2c_pca9557_read(int type)
253 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
254 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
258 val = (val & 0x10) >> 4;
260 case I2C_READ_PCB_VER:
261 val = ((val & 0x60) >> 5) + 1;
273 struct cpu_type *cpu;
274 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
278 #if defined(CONFIG_TARGET_P1010RDB_PA)
279 printf("Board: %sRDB-PA, ", cpu->name);
280 #elif defined(CONFIG_TARGET_P1010RDB_PB)
281 printf("Board: %sRDB-PB, ", cpu->name);
282 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
283 i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
284 val = 0x0; /* no polarity inversion */
285 i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
289 /* switch to IFC to read info from CPLD */
290 config_board_mux(MUX_TYPE_IFC);
293 #if defined(CONFIG_TARGET_P1010RDB_PA)
294 val = (in_8(&cpld_data->pcba_ver) & 0xf);
295 printf("PCB: v%x.0\n", val);
296 #elif defined(CONFIG_TARGET_P1010RDB_PB)
297 val = in_8(&cpld_data->cpld_ver);
298 printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
299 printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
300 val = in_8(&cpld_data->rom_loc) & 0xf;
304 config_board_mux(MUX_TYPE_CS0_NOR);
305 printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
309 val = 0x60; /* set pca9557 pin input/output */
310 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
313 config_board_mux(MUX_TYPE_IFC);
314 config_board_mux(MUX_TYPE_CS0_NAND);
318 config_board_mux(MUX_TYPE_IFC);
329 int board_eth_init(bd_t *bis)
331 #ifdef CONFIG_TSEC_ENET
332 struct fsl_pq_mdio_info mdio_info;
333 struct tsec_info_struct tsec_info[4];
334 struct cpu_type *cpu;
340 SET_STD_TSEC_INFO(tsec_info[num], 1);
344 SET_STD_TSEC_INFO(tsec_info[num], 2);
348 /* P1014 and it's derivatives do not support eTSEC3 */
349 if (cpu->soc_ver != SVR_P1014) {
350 SET_STD_TSEC_INFO(tsec_info[num], 3);
355 printf("No TSECs initialized\n");
359 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
360 mdio_info.name = DEFAULT_MII_NAME;
362 fsl_pq_mdio_init(bis, &mdio_info);
364 tsec_eth_init(bis, tsec_info, num);
367 return pci_eth_init(bis);
370 #if defined(CONFIG_OF_BOARD_SETUP)
371 void fdt_del_flexcan(void *blob)
375 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
376 "fsl,p1010-flexcan")) >= 0) {
377 fdt_del_node(blob, nodeoff);
381 void fdt_del_spi_flash(void *blob)
385 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
386 "spansion,s25sl12801")) >= 0) {
387 fdt_del_node(blob, nodeoff);
391 void fdt_del_spi_slic(void *blob)
395 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
396 "zarlink,le88266")) >= 0) {
397 fdt_del_node(blob, nodeoff);
401 void fdt_del_tdm(void *blob)
405 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
406 "fsl,starlite-tdm")) >= 0) {
407 fdt_del_node(blob, nodeoff);
411 void fdt_del_sdhc(void *blob)
415 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
416 "fsl,esdhc")) >= 0) {
417 fdt_del_node(blob, nodeoff);
421 void fdt_del_ifc(void *blob)
425 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
427 fdt_del_node(blob, nodeoff);
431 void fdt_disable_uart1(void *blob)
435 nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
436 CONFIG_SYS_NS16550_COM2);
439 fdt_status_disabled(blob, nodeoff);
441 printf("WARNING unable to set status for fsl,ns16550 "
442 "uart1: %s\n", fdt_strerror(nodeoff));
446 int ft_board_setup(void *blob, bd_t *bd)
450 struct cpu_type *cpu;
454 ft_cpu_setup(blob, bd);
456 base = env_get_bootm_low();
457 size = env_get_bootm_size();
459 #if defined(CONFIG_PCI)
463 fdt_fixup_memory(blob, (u64)base, (u64)size);
465 #if defined(CONFIG_HAS_FSL_DR_USB)
466 fsl_fdt_fixup_dr_usb(blob, bd);
469 /* P1014 and it's derivatives don't support CAN and eTSEC3 */
470 if (cpu->soc_ver == SVR_P1014) {
471 fdt_del_flexcan(blob);
472 fdt_del_node_and_alias(blob, "ethernet2");
475 /* Delete IFC node as IFC pins are multiplexing with SDHC */
476 if (sd_ifc_mux != MUX_TYPE_IFC)
481 if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
483 fdt_del_spi_slic(blob);
484 } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
485 fdt_del_flexcan(blob);
486 fdt_del_spi_flash(blob);
487 fdt_disable_uart1(blob);
490 * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
491 * explicitly, defaultly spi_cs_sel to spi-flash instead of
495 fdt_del_flexcan(blob);
496 fdt_disable_uart1(blob);
504 int board_mmc_init(bd_t *bis)
506 config_board_mux(MUX_TYPE_SDHC);
510 void board_reset(void)
512 /* mux to IFC to enable CPLD for reset */
513 if (sd_ifc_mux != MUX_TYPE_IFC)
514 config_board_mux(MUX_TYPE_IFC);
519 int misc_init_r(void)
521 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
523 if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
524 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
525 MPC85xx_PMUXCR_CAN1_UART |
526 MPC85xx_PMUXCR_CAN2_TDM |
527 MPC85xx_PMUXCR_CAN2_UART);
528 config_board_mux(MUX_TYPE_CAN);
529 } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
530 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
531 MPC85xx_PMUXCR_CAN1_UART);
532 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
533 MPC85xx_PMUXCR_CAN1_TDM);
534 clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
535 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
536 config_board_mux(MUX_TYPE_TDM);
538 /* defaultly spi_cs_sel to flash */
539 config_board_mux(MUX_TYPE_SPIFLASH);
542 if (hwconfig("esdhc"))
543 config_board_mux(MUX_TYPE_SDHC);
544 else if (hwconfig("ifc"))
545 config_board_mux(MUX_TYPE_IFC);
547 #ifdef CONFIG_TARGET_P1010RDB_PB
548 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
553 #ifndef CONFIG_SPL_BUILD
554 static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
558 return CMD_RET_USAGE;
559 if (strcmp(argv[1], "ifc") == 0)
560 config_board_mux(MUX_TYPE_IFC);
561 else if (strcmp(argv[1], "sdhc") == 0)
562 config_board_mux(MUX_TYPE_SDHC);
564 return CMD_RET_USAGE;
569 mux, 2, 0, pin_mux_cmd,
570 "configure multiplexing pin for IFC/SDHC bus in runtime",
571 "bus_type (e.g. mux sdhc)"