2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
26 #include <asm/cache.h>
27 #include <asm/immap_85xx.h>
31 #include <fdt_support.h>
37 #include <asm/fsl_serdes.h>
38 #include <asm/fsl_ifc.h>
39 #include <asm/fsl_pci.h>
45 DECLARE_GLOBAL_DATA_PTR;
47 #define GPIO4_PCIE_RESET_SET 0x08000000
48 #define MUX_CPLD_CAN_UART 0x00
49 #define MUX_CPLD_TDM 0x01
50 #define MUX_CPLD_SPICS0_FLASH 0x00
51 #define MUX_CPLD_SPICS0_SLIC 0x02
55 u8 cpld_ver; /* cpld revision */
56 u8 pcba_ver; /* pcb revision number */
59 u8 bank_sel; /* NOR Flash bank */
65 u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
66 u8 por0; /* POR Options */
67 u8 por1; /* POR Options */
68 u8 por2; /* POR Options */
69 u8 por3; /* POR Options */
74 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
76 printf("CPLD: V%x.%x PCBA: V%x.0\n",
77 in_8(&cpld_data->cpld_ver) & 0xF0,
78 in_8(&cpld_data->cpld_ver) & 0x0F,
79 in_8(&cpld_data->pcba_ver) & 0x0F);
82 printf("twindie_ddr =%x\n",
83 in_8(&cpld_data->twindie_ddr3));
84 printf("bank_sel =%x\n",
85 in_8(&cpld_data->bank_sel));
86 printf("usb2_sel =%x\n",
87 in_8(&cpld_data->usb2_sel));
88 printf("porsw_sel =%x\n",
89 in_8(&cpld_data->porsw_sel));
90 printf("tdm_can_sel =%x\n",
91 in_8(&cpld_data->tdm_can_sel));
92 printf("tdm_can_sel =%x\n",
93 in_8(&cpld_data->tdm_can_sel));
94 printf("spi_cs0_sel =%x\n",
95 in_8(&cpld_data->spi_cs0_sel));
97 in_8(&cpld_data->bcsr0));
99 in_8(&cpld_data->bcsr1));
100 printf("bcsr2 =%x\n",
101 in_8(&cpld_data->bcsr2));
102 printf("bcsr3 =%x\n",
103 in_8(&cpld_data->bcsr3));
108 int board_early_init_f(void)
110 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
111 #ifndef CONFIG_SDCARD
112 struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
114 /* Clock configuration to access CPLD using IFC(GPCM) */
115 setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
118 * Reset PCIe slots via GPIO4
120 setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
121 setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
126 int board_early_init_r(void)
128 #ifndef CONFIG_SDCARD
129 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
130 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
133 * Remap Boot flash region to caching-inhibited
134 * so that flash can be erased properly.
137 /* Flush d-cache and invalidate i-cache of any FLASH data */
141 /* invalidate existing TLB entry for flash */
142 disable_tlb(flash_esel);
144 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
145 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
146 0, flash_esel, BOOKE_PAGESZ_16M, 1);
148 set_tlb(1, flashbase + 0x1000000,
149 CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
150 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
151 0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
157 void pci_init_board(void)
159 fsl_pcie_init_board(0);
161 #endif /* ifdef CONFIG_PCI */
165 struct cpu_type *cpu;
168 printf("Board: %sRDB\n", cpu->name);
173 #ifdef CONFIG_TSEC_ENET
174 int board_eth_init(bd_t *bis)
176 struct fsl_pq_mdio_info mdio_info;
177 struct tsec_info_struct tsec_info[4];
178 struct cpu_type *cpu;
184 SET_STD_TSEC_INFO(tsec_info[num], 1);
188 SET_STD_TSEC_INFO(tsec_info[num], 2);
192 /* P1014 and it's derivatives do not support eTSEC3 */
193 if (cpu->soc_ver != SVR_P1014) {
194 SET_STD_TSEC_INFO(tsec_info[num], 3);
199 printf("No TSECs initialized\n");
203 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
204 mdio_info.name = DEFAULT_MII_NAME;
206 fsl_pq_mdio_init(bis, &mdio_info);
208 tsec_eth_init(bis, tsec_info, num);
210 return pci_eth_init(bis);
214 #if defined(CONFIG_OF_BOARD_SETUP)
215 void fdt_del_flexcan(void *blob)
219 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
220 "fsl,p1010-flexcan")) >= 0) {
221 fdt_del_node(blob, nodeoff);
225 void fdt_del_spi_flash(void *blob)
229 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
230 "spansion,s25sl12801")) >= 0) {
231 fdt_del_node(blob, nodeoff);
235 void fdt_del_spi_slic(void *blob)
239 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
240 "zarlink,le88266")) >= 0) {
241 fdt_del_node(blob, nodeoff);
245 void fdt_del_tdm(void *blob)
249 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
250 "fsl,starlite-tdm")) >= 0) {
251 fdt_del_node(blob, nodeoff);
255 void fdt_del_sdhc(void *blob)
259 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
260 "fsl,esdhc")) >= 0) {
261 fdt_del_node(blob, nodeoff);
265 void fdt_disable_uart1(void *blob)
269 nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
270 CONFIG_SYS_NS16550_COM2);
273 fdt_status_disabled(blob, nodeoff);
275 printf("WARNING unable to set status for fsl,ns16550 "
276 "uart1: %s\n", fdt_strerror(nodeoff));
280 void ft_board_setup(void *blob, bd_t *bd)
284 struct cpu_type *cpu;
288 ft_cpu_setup(blob, bd);
290 base = getenv_bootm_low();
291 size = getenv_bootm_size();
293 #if defined(CONFIG_PCI)
297 fdt_fixup_memory(blob, (u64)base, (u64)size);
299 #if defined(CONFIG_HAS_FSL_DR_USB)
300 fdt_fixup_dr_usb(blob, bd);
303 /* P1014 and it's derivatives don't support CAN and eTSEC3 */
304 if (cpu->soc_ver == SVR_P1014) {
305 fdt_del_flexcan(blob);
306 fdt_del_node_and_alias(blob, "ethernet2");
308 #ifndef CONFIG_SDCARD
309 /* disable sdhc due to sdhc bug */
311 if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
313 fdt_del_spi_slic(blob);
314 } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
315 fdt_del_flexcan(blob);
316 fdt_del_spi_flash(blob);
317 fdt_disable_uart1(blob);
320 * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
321 * explicitly, defaultly spi_cs_sel to spi-flash instead of
325 fdt_del_flexcan(blob);
326 fdt_disable_uart1(blob);
332 #ifndef CONFIG_SDCARD
333 int misc_init_r(void)
335 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
336 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
338 if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
339 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
340 MPC85xx_PMUXCR_CAN1_UART |
341 MPC85xx_PMUXCR_CAN2_TDM |
342 MPC85xx_PMUXCR_CAN2_UART);
343 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
344 } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
345 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
346 MPC85xx_PMUXCR_CAN1_UART);
347 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
348 MPC85xx_PMUXCR_CAN1_TDM);
349 clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
350 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
351 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
352 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
354 /* defaultly spi_cs_sel to flash */
355 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);