2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 * Authors: Timur Tabi <timur@freescale.com>
5 * FSL DIU Framebuffer driver
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
16 #include <stdio_dev.h>
18 #include "../common/ngpixis.h"
19 #include <fsl_diu_fb.h>
21 /* The CTL register is called 'csr' in the ngpixis_t structure */
22 #define PX_CTL_ALTACC 0x80
24 #define PX_BRDCFG0_ELBC_SPI_MASK 0xc0
25 #define PX_BRDCFG0_ELBC_SPI_ELBC 0x00
26 #define PX_BRDCFG0_ELBC_SPI_NULL 0xc0
27 #define PX_BRDCFG0_ELBC_DIU 0x02
29 #define PX_BRDCFG1_DVIEN 0x80
30 #define PX_BRDCFG1_DFPEN 0x40
31 #define PX_BRDCFG1_BACKLIGHT 0x20
33 #define PMUXCR_ELBCDIU_MASK 0xc0000000
34 #define PMUXCR_ELBCDIU_NOR16 0x80000000
35 #define PMUXCR_ELBCDIU_DIU 0x40000000
40 * Note that we need to byte-swap the value before it's written to the AD
41 * register. So even though the registers don't look like they're in the same
42 * bit positions as they are on the MPC8610, the same value is written to the
43 * AD register on the MPC8610 and on the P1022.
45 #define AD_BYTE_F 0x10000000
46 #define AD_ALPHA_C_SHIFT 25
47 #define AD_BLUE_C_SHIFT 23
48 #define AD_GREEN_C_SHIFT 21
49 #define AD_RED_C_SHIFT 19
50 #define AD_PIXEL_S_SHIFT 16
51 #define AD_COMP_3_SHIFT 12
52 #define AD_COMP_2_SHIFT 8
53 #define AD_COMP_1_SHIFT 4
54 #define AD_COMP_0_SHIFT 0
57 * Variables used by the DIU/LBC switching code. It's safe to makes these
58 * global, because the DIU requires DDR, so we'll only run this code after
63 static void *lbc_lcs0_ba;
64 static void *lbc_lcs1_ba;
66 void diu_set_pixel_clock(unsigned int pixclock)
68 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
69 unsigned long speed_ccb, temp;
72 speed_ccb = get_bus_freq(0);
73 temp = 1000000000 / pixclock;
75 pixval = speed_ccb / temp;
76 debug("DIU pixval = %lu\n", pixval);
78 /* Modify PXCLK in GUTS CLKDVDR */
79 temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
80 out_be32(&gur->clkdvdr, temp); /* turn off clock */
81 out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
84 int platform_diu_init(unsigned int *xres, unsigned int *yres)
86 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
91 /* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */
92 lbc_lcs0_ba = (void *)(get_lbc_br(0) & get_lbc_or(0) & 0xFFFF8000);
93 lbc_lcs1_ba = (void *)(get_lbc_br(1) & get_lbc_or(1) & 0xFFFF8000);
95 pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
96 (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
97 (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
98 (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
99 (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
101 temp = in_8(&pixis->brdcfg1);
103 monitor_port = getenv("monitor");
104 if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */
107 /* Enable the DFP port, disable the DVI and the backlight */
108 temp &= ~(PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT);
109 temp |= PX_BRDCFG1_DFPEN;
113 /* Enable the DVI port, disable the DFP and the backlight */
114 temp &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
115 temp |= PX_BRDCFG1_DVIEN;
118 out_8(&pixis->brdcfg1, temp);
121 * Enable PIXIS indirect access mode. This is a hack that allows us to
122 * access PIXIS registers even when the LBC pins have been muxed to the
125 setbits_8(&pixis->csr, PX_CTL_ALTACC);
128 * Route the LAD pins to the DIU. This will disable access to the eLBC,
129 * which means we won't be able to read/write any NOR flash addresses!
131 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
132 px_brdcfg0 = in_8(lbc_lcs1_ba);
133 out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
135 /* Set PMUXCR to switch the muxed pins from the LBC to the DIU */
136 clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
137 pmuxcr = in_be32(&gur->pmuxcr);
139 return fsl_diu_init(*xres, pixel_format, 0);
143 * set_mux_to_lbc - disable the DIU so that we can read/write to elbc
145 * On the Freescale P1022, the DIU video signal and the LBC address/data lines
146 * share the same pins, which means that when the DIU is active (e.g. the
147 * console is on the DVI display), NOR flash cannot be accessed. So we use the
148 * weak accessor feature of the CFI flash code to temporarily switch the pin
149 * mux from DIU to LBC whenever we want to read or write flash. This has a
150 * significant performance penalty, but it's the only way to make it work.
152 * There are two muxes: one on the chip, and one on the board. The chip mux
153 * controls whether the pins are used for the DIU or the LBC, and it is
154 * set via PMUXCR. The board mux controls whether those signals go to
155 * the video connector or the NOR flash chips, and it is set via the ngPIXIS.
157 static int set_mux_to_lbc(void)
159 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
161 /* Switch the muxes only if they're currently set to DIU mode */
162 if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
163 PMUXCR_ELBCDIU_NOR16) {
165 * In DIU mode, the PIXIS can only be accessed indirectly
166 * since we can't read/write the LBC directly.
169 /* Set the board mux to LBC. This will disable the display. */
170 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
171 px_brdcfg0 = in_8(lbc_lcs1_ba);
172 out_8(lbc_lcs1_ba, (px_brdcfg0 & ~(PX_BRDCFG0_ELBC_SPI_MASK
173 | PX_BRDCFG0_ELBC_DIU)) | PX_BRDCFG0_ELBC_SPI_ELBC);
175 /* Disable indirect PIXIS mode */
176 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, csr));
177 clrbits_8(lbc_lcs1_ba, PX_CTL_ALTACC);
179 /* Set the chip mux to LBC mode, so that writes go to flash. */
180 out_be32(&gur->pmuxcr, (pmuxcr & ~PMUXCR_ELBCDIU_MASK) |
181 PMUXCR_ELBCDIU_NOR16);
182 in_be32(&gur->pmuxcr);
191 * set_mux_to_diu - re-enable the DIU muxing
193 * This function restores the chip and board muxing to point to the DIU.
195 static void set_mux_to_diu(void)
197 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
199 /* Enable indirect PIXIS mode */
200 setbits_8(&pixis->csr, PX_CTL_ALTACC);
202 /* Set the board mux to DIU. This will enable the display. */
203 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
204 out_8(lbc_lcs1_ba, px_brdcfg0);
207 /* Set the chip mux to DIU mode. */
208 out_be32(&gur->pmuxcr, pmuxcr);
209 in_be32(&gur->pmuxcr);
213 * pixis_read - board-specific function to read from the PIXIS
215 * This function overrides the generic pixis_read() function, so that it can
216 * use PIXIS indirect mode if necessary.
218 u8 pixis_read(unsigned int reg)
220 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
222 /* Use indirect mode if the mux is currently set to DIU mode */
223 if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
224 PMUXCR_ELBCDIU_NOR16) {
225 out_8(lbc_lcs0_ba, reg);
226 return in_8(lbc_lcs1_ba);
228 void *p = (void *)PIXIS_BASE;
230 return in_8(p + reg);
235 * pixis_write - board-specific function to write to the PIXIS
237 * This function overrides the generic pixis_write() function, so that it can
238 * use PIXIS indirect mode if necessary.
240 void pixis_write(unsigned int reg, u8 value)
242 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
244 /* Use indirect mode if the mux is currently set to DIU mode */
245 if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
246 PMUXCR_ELBCDIU_NOR16) {
247 out_8(lbc_lcs0_ba, reg);
248 out_8(lbc_lcs1_ba, value);
249 /* Do a read-back to ensure the write completed */
252 void *p = (void *)PIXIS_BASE;
254 out_8(p + reg, value);
258 void pixis_bank_reset(void)
261 * For some reason, a PIXIS bank reset does not work if the PIXIS is
262 * in indirect mode, so switch to direct mode first.
266 out_8(&pixis->vctl, 0);
267 out_8(&pixis->vctl, 1);
272 #ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
274 void flash_write8(u8 value, void *addr)
276 int sw = set_mux_to_lbc();
278 __raw_writeb(value, addr);
281 * To ensure the post-write is completed to eLBC, software must
282 * perform a dummy read from one valid address from eLBC space
283 * before changing the eLBC_DIU from NOR mode to DIU mode.
284 * set_mux_to_diu() includes a sync that will ensure the
285 * __raw_readb() completes before it switches the mux.
292 void flash_write16(u16 value, void *addr)
294 int sw = set_mux_to_lbc();
296 __raw_writew(value, addr);
299 * To ensure the post-write is completed to eLBC, software must
300 * perform a dummy read from one valid address from eLBC space
301 * before changing the eLBC_DIU from NOR mode to DIU mode.
302 * set_mux_to_diu() includes a sync that will ensure the
303 * __raw_readb() completes before it switches the mux.
310 void flash_write32(u32 value, void *addr)
312 int sw = set_mux_to_lbc();
314 __raw_writel(value, addr);
317 * To ensure the post-write is completed to eLBC, software must
318 * perform a dummy read from one valid address from eLBC space
319 * before changing the eLBC_DIU from NOR mode to DIU mode.
320 * set_mux_to_diu() includes a sync that will ensure the
321 * __raw_readb() completes before it switches the mux.
328 void flash_write64(u64 value, void *addr)
330 int sw = set_mux_to_lbc();
334 * There is no __raw_writeq(), so do the write manually. We don't trust
335 * the compiler, so we use inline assembly.
337 __asm__ __volatile__(
340 : "=m" (*p), "=m" (*(p + 1))
341 : "r" ((uint32_t) (value >> 32)), "r" ((uint32_t) (value)));
345 * To ensure the post-write is completed to eLBC, software must
346 * perform a dummy read from one valid address from eLBC space
347 * before changing the eLBC_DIU from NOR mode to DIU mode. We
348 * read addr+4 because we just wrote to addr+4, so that's how we
349 * maintain execution order. set_mux_to_diu() includes a sync
350 * that will ensure the __raw_readb() completes before it
353 __raw_readb(addr + 4);
358 u8 flash_read8(void *addr)
362 int sw = set_mux_to_lbc();
364 ret = __raw_readb(addr);
371 u16 flash_read16(void *addr)
375 int sw = set_mux_to_lbc();
377 ret = __raw_readw(addr);
384 u32 flash_read32(void *addr)
388 int sw = set_mux_to_lbc();
390 ret = __raw_readl(addr);
397 u64 flash_read64(void *addr)
401 int sw = set_mux_to_lbc();
403 /* There is no __raw_readq(), so do the read manually */
404 ret = *(volatile u64 *)addr;