2 * Copyright 2010 Freescale Semiconductor, Inc.
3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4 * Timur Tabi <timur@freescale.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the Free
8 * Software Foundation; either version 2 of the License, or (at your option)
15 #include <asm/processor.h>
17 #include <asm/cache.h>
18 #include <asm/immap_85xx.h>
19 #include <asm/fsl_pci.h>
20 #include <asm/fsl_ddr_sdram.h>
21 #include <asm/fsl_serdes.h>
24 #include <fdt_support.h>
26 #include <asm/fsl_law.h>
32 #include "../common/ngpixis.h"
34 DECLARE_GLOBAL_DATA_PTR;
36 int board_early_init_f(void)
38 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
40 /* Set pmuxcr to allow both i2c1 and i2c2 */
41 setbits_be32(&gur->pmuxcr, 0x1000);
43 /* Read back the register to synchronize the write. */
44 in_be32(&gur->pmuxcr);
46 /* Set the pin muxing to enable ETSEC2. */
47 clrbits_be32(&gur->pmuxcr2, 0x001F8000);
56 puts("Board: P1022DS ");
58 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
59 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
61 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
63 switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
65 printf ("vBank: %u\n", ((sw & 0x30) >> 4));
79 #define CONFIG_TFP410_I2C_ADDR 0x38
81 /* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
82 #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c
83 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03
85 /* Route the I2C1 pins to the SSI port instead. */
86 #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08
88 /* Choose the 12.288Mhz codec reference clock */
89 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02
91 /* Choose the 11.2896Mhz codec reference clock */
92 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01
100 /* For DVI, enable the TFP410 Encoder. */
103 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
105 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
107 debug("DVI Encoder Read: 0x%02x\n", temp);
110 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
112 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
114 debug("DVI Encoder Read: 0x%02x\n",temp);
117 * Enable the reference clock for the WM8776 codec, and route the MUX
118 * pins for SSI. The default is the 12.288 MHz clock
121 temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
122 CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
123 temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
125 audclk = hwconfig_arg("audclk", &arglen);
126 /* Check the first two chars only */
127 if (audclk && (strncmp(audclk, "11", 2) == 0))
128 temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
130 temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
131 out_8(&pixis->brdcfg1, temp);
137 * A list of PCI and SATA slots
150 * This array maps the slot identifiers to their names on the P1022DS board.
152 static const char *slot_names[] = {
153 [SLOT_PCIE1] = "Slot 1",
154 [SLOT_PCIE2] = "Slot 2",
155 [SLOT_PCIE3] = "Slot 3",
156 [SLOT_PCIE4] = "Slot 4",
157 [SLOT_PCIE5] = "Mini-PCIe",
158 [SLOT_SATA1] = "SATA 1",
159 [SLOT_SATA2] = "SATA 2",
163 * This array maps a given SERDES configuration and SERDES device to the PCI or
164 * SATA slot that it connects to. This mapping is hard-coded in the FPGA.
166 static u8 serdes_dev_slot[][SATA2 + 1] = {
167 [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
168 [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
169 [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
170 [PCIE2] = SLOT_PCIE5 },
171 [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
172 [PCIE2] = SLOT_PCIE3,
173 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
174 [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
175 [PCIE2] = SLOT_PCIE3 },
176 [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
177 [PCIE2] = SLOT_PCIE3,
178 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
179 [0x1c] = { [PCIE1] = SLOT_PCIE1,
180 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
181 [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
182 [0x1f] = { [PCIE1] = SLOT_PCIE1 },
187 * Returns the name of the slot to which the PCIe or SATA controller is
190 const char *board_serdes_name(enum srds_prtcl device)
192 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
193 u32 pordevsr = in_be32(&gur->pordevsr);
194 unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
195 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
196 enum slot_id slot = serdes_dev_slot[srds_cfg][device];
197 const char *name = slot_names[slot];
206 void pci_init_board(void)
208 fsl_pcie_init_board(0);
212 int board_early_init_r(void)
214 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
215 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
218 * Remap Boot flash + PROMJET region to caching-inhibited
219 * so that flash can be erased properly.
222 /* Flush d-cache and invalidate i-cache of any FLASH data */
226 /* invalidate existing TLB entry for flash + promjet */
227 disable_tlb(flash_esel);
229 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
230 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
231 0, flash_esel, BOOKE_PAGESZ_256M, 1);
237 * Initialize on-board and/or PCI Ethernet devices
241 * 0, no ethernet devices found
242 * >0, number of ethernet devices initialized
244 int board_eth_init(bd_t *bis)
246 struct tsec_info_struct tsec_info[2];
247 unsigned int num = 0;
250 SET_STD_TSEC_INFO(tsec_info[num], 1);
254 SET_STD_TSEC_INFO(tsec_info[num], 2);
258 return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
261 #ifdef CONFIG_OF_BOARD_SETUP
263 * ft_codec_setup - fix up the clock-frequency property of the codec node
265 * Update the clock-frequency property based on the value of the 'audclk'
266 * hwconfig option. If audclk is not specified, then default to 12.288MHz.
268 static void ft_codec_setup(void *blob, const char *compatible)
274 audclk = hwconfig_arg("audclk", &arglen);
275 if (audclk && (strncmp(audclk, "11", 2) == 0))
280 do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1);
283 void ft_board_setup(void *blob, bd_t *bd)
288 ft_cpu_setup(blob, bd);
290 base = getenv_bootm_low();
291 size = getenv_bootm_size();
293 fdt_fixup_memory(blob, (u64)base, (u64)size);
297 #ifdef CONFIG_FSL_SGMII_RISER
298 fsl_sgmii_riser_fdt_fixup(blob);
301 /* Update the WM8776 node's clock frequency property */
302 ft_codec_setup(blob, "wlf,wm8776");
307 void board_lmb_reserve(struct lmb *lmb)
309 cpu_mp_lmb_reserve(lmb);