2 * Copyright 2010 Freescale Semiconductor, Inc.
3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4 * Timur Tabi <timur@freescale.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the Free
8 * Software Foundation; either version 2 of the License, or (at your option)
15 #include <asm/processor.h>
17 #include <asm/cache.h>
18 #include <asm/immap_85xx.h>
19 #include <asm/fsl_pci.h>
20 #include <asm/fsl_ddr_sdram.h>
21 #include <asm/fsl_serdes.h>
24 #include <fdt_support.h>
26 #include <asm/fsl_law.h>
31 #include "../common/ngpixis.h"
33 DECLARE_GLOBAL_DATA_PTR;
35 int board_early_init_f(void)
37 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
39 /* Set pmuxcr to allow both i2c1 and i2c2 */
40 setbits_be32(&gur->pmuxcr, 0x1000);
42 /* Read back the register to synchronize the write. */
43 in_be32(&gur->pmuxcr);
45 /* Set the pin muxing to enable ETSEC2. */
46 clrbits_be32(&gur->pmuxcr2, 0x001F8000);
55 puts("Board: P1022DS ");
57 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
58 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
60 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
62 switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
64 printf ("vBank: %u\n", ((sw & 0x30) >> 4));
78 phys_size_t initdram(int board_type)
80 phys_size_t dram_size = 0;
82 puts("Initializing....\n");
84 dram_size = fsl_ddr_sdram();
85 dram_size = setup_ddr_tlbs(dram_size / 0x100000) * 0x100000;
91 #define CONFIG_TFP410_I2C_ADDR 0x38
97 /* Enable the TFP410 Encoder */
100 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
103 /* Verify if enabled */
105 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
108 debug("DVI Encoder Read: 0x%02x\n", temp);
111 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
114 /* Verify if enabled */
116 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
119 debug("DVI Encoder Read: 0x%02x\n",temp);
125 * A list of PCI and SATA slots
138 * This array maps the slot identifiers to their names on the P1022DS board.
140 static const char *slot_names[] = {
141 [SLOT_PCIE1] = "Slot 1",
142 [SLOT_PCIE2] = "Slot 2",
143 [SLOT_PCIE3] = "Slot 3",
144 [SLOT_PCIE4] = "Slot 4",
145 [SLOT_PCIE5] = "Mini-PCIe",
146 [SLOT_SATA1] = "SATA 1",
147 [SLOT_SATA2] = "SATA 2",
151 * This array maps a given SERDES configuration and SERDES device to the PCI or
152 * SATA slot that it connects to. This mapping is hard-coded in the FPGA.
154 static u8 serdes_dev_slot[][SATA2 + 1] = {
155 [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
156 [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
157 [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
158 [PCIE2] = SLOT_PCIE5 },
159 [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
160 [PCIE2] = SLOT_PCIE3,
161 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
162 [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
163 [PCIE2] = SLOT_PCIE3 },
164 [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
165 [PCIE2] = SLOT_PCIE3,
166 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
167 [0x1c] = { [PCIE1] = SLOT_PCIE1,
168 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
169 [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
170 [0x1f] = { [PCIE1] = SLOT_PCIE1 },
175 * Returns the name of the slot to which the PCIe or SATA controller is
178 const char *serdes_slot_name(enum srds_prtcl device)
180 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
181 u32 pordevsr = in_be32(&gur->pordevsr);
182 unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
183 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
184 enum slot_id slot = serdes_dev_slot[srds_cfg][device];
185 const char *name = slot_names[slot];
193 static void configure_pcie(struct fsl_pci_info *info,
194 struct pci_controller *hose,
195 const char *connected)
197 static int bus_number = 0;
200 set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
201 set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
202 is_endpoint = fsl_setup_hose(hose, info->regs);
203 printf(" PCIE%u connected to %s as %s (base addr %lx)\n",
204 info->pci_num, connected,
205 is_endpoint ? "Endpoint" : "Root Complex", info->regs);
206 bus_number = fsl_pci_init_port(info, hose, bus_number);
210 static struct pci_controller pcie1_hose;
214 static struct pci_controller pcie2_hose;
218 static struct pci_controller pcie3_hose;
222 void pci_init_board(void)
224 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
225 struct fsl_pci_info pci_info;
226 u32 devdisr = in_be32(&gur->devdisr);
229 if (is_serdes_configured(PCIE1) && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
230 SET_STD_PCIE_INFO(pci_info, 1);
231 configure_pcie(&pci_info, &pcie1_hose, serdes_slot_name(PCIE1));
233 printf(" PCIE1: disabled\n");
236 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
240 if (is_serdes_configured(PCIE2) && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
241 SET_STD_PCIE_INFO(pci_info, 2);
242 configure_pcie(&pci_info, &pcie2_hose, serdes_slot_name(PCIE2));
244 printf(" PCIE2: disabled\n");
247 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
251 if (is_serdes_configured(PCIE3) && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
252 SET_STD_PCIE_INFO(pci_info, 3);
253 configure_pcie(&pci_info, &pcie3_hose, serdes_slot_name(PCIE3));
255 printf(" PCIE3: disabled\n");
258 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
263 int board_early_init_r(void)
265 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
266 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
269 * Remap Boot flash + PROMJET region to caching-inhibited
270 * so that flash can be erased properly.
273 /* Flush d-cache and invalidate i-cache of any FLASH data */
277 /* invalidate existing TLB entry for flash + promjet */
278 disable_tlb(flash_esel);
280 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
281 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
282 0, flash_esel, BOOKE_PAGESZ_256M, 1);
288 * Initialize on-board and/or PCI Ethernet devices
292 * 0, no ethernet devices found
293 * >0, number of ethernet devices initialized
295 int board_eth_init(bd_t *bis)
297 struct tsec_info_struct tsec_info[2];
298 unsigned int num = 0;
301 SET_STD_TSEC_INFO(tsec_info[num], 1);
305 SET_STD_TSEC_INFO(tsec_info[num], 2);
309 return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
312 #ifdef CONFIG_OF_BOARD_SETUP
313 void ft_board_setup(void *blob, bd_t *bd)
318 ft_cpu_setup(blob, bd);
320 base = getenv_bootm_low();
321 size = getenv_bootm_size();
323 fdt_fixup_memory(blob, (u64)base, (u64)size);
327 #ifdef CONFIG_FSL_SGMII_RISER
328 fsl_sgmii_riser_fdt_fixup(blob);
334 void board_lmb_reserve(struct lmb *lmb)
336 cpu_mp_lmb_reserve(lmb);