2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4 * Timur Tabi <timur@freescale.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the Free
8 * Software Foundation; either version 2 of the License, or (at your option)
15 #include <asm/processor.h>
17 #include <asm/cache.h>
18 #include <asm/immap_85xx.h>
19 #include <asm/fsl_pci.h>
20 #include <asm/fsl_ddr_sdram.h>
21 #include <asm/fsl_serdes.h>
24 #include <fdt_support.h>
26 #include <asm/fsl_law.h>
31 #include "../common/ngpixis.h"
33 DECLARE_GLOBAL_DATA_PTR;
35 int board_early_init_f(void)
37 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
39 /* Set pmuxcr to allow both i2c1 and i2c2 */
40 setbits_be32(&gur->pmuxcr, 0x1000);
42 /* Read back the register to synchronize the write. */
43 in_be32(&gur->pmuxcr);
45 /* Set the pin muxing to enable ETSEC2. */
46 clrbits_be32(&gur->pmuxcr2, 0x001F8000);
55 puts("Board: P1022DS ");
57 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
58 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
60 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
62 switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
64 printf ("vBank: %u\n", ((sw & 0x30) >> 4));
78 #define CONFIG_TFP410_I2C_ADDR 0x38
80 /* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
81 #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c
82 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03
84 /* Route the I2C1 pins to the SSI port instead. */
85 #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08
87 /* Choose the 12.288Mhz codec reference clock */
88 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02
90 /* Choose the 11.2896Mhz codec reference clock */
91 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01
99 /* For DVI, enable the TFP410 Encoder. */
102 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
104 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
106 debug("DVI Encoder Read: 0x%02x\n", temp);
109 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
111 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
113 debug("DVI Encoder Read: 0x%02x\n",temp);
116 * Enable the reference clock for the WM8776 codec, and route the MUX
117 * pins for SSI. The default is the 12.288 MHz clock
120 temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
121 CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
122 temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
124 audclk = hwconfig_arg("audclk", &arglen);
125 /* Check the first two chars only */
126 if (audclk && (strncmp(audclk, "11", 2) == 0))
127 temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
129 temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
130 out_8(&pixis->brdcfg1, temp);
136 * A list of PCI and SATA slots
149 * This array maps the slot identifiers to their names on the P1022DS board.
151 static const char *slot_names[] = {
152 [SLOT_PCIE1] = "Slot 1",
153 [SLOT_PCIE2] = "Slot 2",
154 [SLOT_PCIE3] = "Slot 3",
155 [SLOT_PCIE4] = "Slot 4",
156 [SLOT_PCIE5] = "Mini-PCIe",
157 [SLOT_SATA1] = "SATA 1",
158 [SLOT_SATA2] = "SATA 2",
162 * This array maps a given SERDES configuration and SERDES device to the PCI or
163 * SATA slot that it connects to. This mapping is hard-coded in the FPGA.
165 static u8 serdes_dev_slot[][SATA2 + 1] = {
166 [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
167 [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
168 [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
169 [PCIE2] = SLOT_PCIE5 },
170 [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
171 [PCIE2] = SLOT_PCIE3,
172 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
173 [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
174 [PCIE2] = SLOT_PCIE3 },
175 [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
176 [PCIE2] = SLOT_PCIE3,
177 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
178 [0x1c] = { [PCIE1] = SLOT_PCIE1,
179 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
180 [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
181 [0x1f] = { [PCIE1] = SLOT_PCIE1 },
186 * Returns the name of the slot to which the PCIe or SATA controller is
189 const char *board_serdes_name(enum srds_prtcl device)
191 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
192 u32 pordevsr = in_be32(&gur->pordevsr);
193 unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
194 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
195 enum slot_id slot = serdes_dev_slot[srds_cfg][device];
196 const char *name = slot_names[slot];
205 void pci_init_board(void)
207 fsl_pcie_init_board(0);
211 int board_early_init_r(void)
213 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
214 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
217 * Remap Boot flash + PROMJET region to caching-inhibited
218 * so that flash can be erased properly.
221 /* Flush d-cache and invalidate i-cache of any FLASH data */
225 /* invalidate existing TLB entry for flash + promjet */
226 disable_tlb(flash_esel);
228 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
229 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
230 0, flash_esel, BOOKE_PAGESZ_256M, 1);
236 * Initialize on-board and/or PCI Ethernet devices
240 * 0, no ethernet devices found
241 * >0, number of ethernet devices initialized
243 int board_eth_init(bd_t *bis)
245 struct tsec_info_struct tsec_info[2];
246 unsigned int num = 0;
249 SET_STD_TSEC_INFO(tsec_info[num], 1);
253 SET_STD_TSEC_INFO(tsec_info[num], 2);
257 return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
260 #ifdef CONFIG_OF_BOARD_SETUP
262 * ft_codec_setup - fix up the clock-frequency property of the codec node
264 * Update the clock-frequency property based on the value of the 'audclk'
265 * hwconfig option. If audclk is not specified, then default to 12.288MHz.
267 static void ft_codec_setup(void *blob, const char *compatible)
273 audclk = hwconfig_arg("audclk", &arglen);
274 if (audclk && (strncmp(audclk, "11", 2) == 0))
279 do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1);
282 void ft_board_setup(void *blob, bd_t *bd)
287 ft_cpu_setup(blob, bd);
289 base = getenv_bootm_low();
290 size = getenv_bootm_size();
292 fdt_fixup_memory(blob, (u64)base, (u64)size);
296 #ifdef CONFIG_FSL_SGMII_RISER
297 fsl_sgmii_riser_fdt_fixup(blob);
300 /* Update the WM8776 node's clock frequency property */
301 ft_codec_setup(blob, "wlf,wm8776");