git.sur5r.net Git - u-boot/blob - board/freescale/p1023rdb/ddr.c

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/mmu.h>
   9 #include <asm/immap_85xx.h>
  10 #include <asm/processor.h>
  11 #include <asm/fsl_ddr_sdram.h>
  12 #include <asm/fsl_ddr_dimm_params.h>
  13 #include <asm/io.h>
  14 #include <asm/fsl_law.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 /* CONFIG_SYS_DDR_RAW_TIMING */
  19 /*
  20  * Hynix H5TQ1G83TFR-H9C
  21  */
  22 dimm_params_t ddr_raw_timing = {
  23         .n_ranks = 1,
  24         .rank_density = 536870912u,
  25         .capacity = 536870912u,
  26         .primary_sdram_width = 32,
  27         .ec_sdram_width = 0,
  28         .registered_dimm = 0,
  29         .mirrored_dimm = 0,
  30         .n_row_addr = 14,
  31         .n_col_addr = 10,
  32         .n_banks_per_sdram_device = 8,
  33         .edc_config = 0,
  34         .burst_lengths_bitmask = 0x0c,
  35
  36         .tckmin_x_ps = 1875,
  37         .caslat_x = 0x1e << 4,  /* 5,6,7,8 */
  38         .taa_ps = 13125,
  39         .twr_ps = 18000,
  40         .trcd_ps = 13125,
  41         .trrd_ps = 7500,
  42         .trp_ps = 13125,
  43         .tras_ps = 37500,
  44         .trc_ps = 50625,
  45         .trfc_ps = 160000,
  46         .twtr_ps = 7500,
  47         .trtp_ps = 7500,
  48         .refresh_rate_ps = 7800000,
  49         .tfaw_ps = 37500,
  50 };
  51
  52 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  53                 unsigned int controller_number,
  54                 unsigned int dimm_number)
  55 {
  56         const char dimm_model[] = "Fixed DDR on board";
  57
  58         if ((controller_number == 0) && (dimm_number == 0)) {
  59                 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  60                 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  61                 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  62         }
  63
  64         return 0;
  65 }
  66
  67 void fsl_ddr_board_options(memctl_options_t *popts,
  68                                 dimm_params_t *pdimm,
  69                                 unsigned int ctrl_num)
  70 {
  71         int i;
  72         popts->clk_adjust = 6;
  73         popts->cpo_override = 0x1f;
  74         popts->write_data_delay = 2;
  75         popts->half_strength_driver_enable = 1;
  76         /* Write leveling override */
  77         popts->wrlvl_en = 1;
  78         popts->wrlvl_override = 1;
  79         popts->wrlvl_sample = 0xf;
  80         popts->wrlvl_start = 0x8;
  81         popts->trwt_override = 1;
  82         popts->trwt = 0;
  83
  84         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  85                 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
  86                 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
  87         }
  88 }