2 * Copyright 2009, 2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/immap_85xx.h>
26 #include <asm/processor.h>
27 #include <asm/fsl_ddr_sdram.h>
29 #include <asm/fsl_law.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
34 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
35 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
36 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
37 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
38 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
39 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x00000000
40 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x00000000
41 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
42 #define CONFIG_SYS_DDR_RCW_1 0x00000000
43 #define CONFIG_SYS_DDR_RCW_2 0x00000000
44 #define CONFIG_SYS_DDR_CONTROL 0x43000000 /* Type = DDR2*/
45 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
46 #define CONFIG_SYS_DDR_TIMING_4 0x00000000
47 #define CONFIG_SYS_DDR_TIMING_5 0x00000000
49 #define CONFIG_SYS_DDR_TIMING_3_400 0x00010000
50 #define CONFIG_SYS_DDR_TIMING_0_400 0x00260802
51 #define CONFIG_SYS_DDR_TIMING_1_400 0x39355322
52 #define CONFIG_SYS_DDR_TIMING_2_400 0x1f9048ca
53 #define CONFIG_SYS_DDR_CLK_CTRL_400 0x02800000
54 #define CONFIG_SYS_DDR_MODE_1_400 0x00480432
55 #define CONFIG_SYS_DDR_MODE_2_400 0x00000000
56 #define CONFIG_SYS_DDR_INTERVAL_400 0x06180100
58 #define CONFIG_SYS_DDR_TIMING_3_533 0x00020000
59 #define CONFIG_SYS_DDR_TIMING_0_533 0x00260802
60 #define CONFIG_SYS_DDR_TIMING_1_533 0x4c47c432
61 #define CONFIG_SYS_DDR_TIMING_2_533 0x0f9848ce
62 #define CONFIG_SYS_DDR_CLK_CTRL_533 0x02800000
63 #define CONFIG_SYS_DDR_MODE_1_533 0x00040642
64 #define CONFIG_SYS_DDR_MODE_2_533 0x00000000
65 #define CONFIG_SYS_DDR_INTERVAL_533 0x08200100
67 #define CONFIG_SYS_DDR_TIMING_3_667 0x00030000
68 #define CONFIG_SYS_DDR_TIMING_0_667 0x55770802
69 #define CONFIG_SYS_DDR_TIMING_1_667 0x5f599543
70 #define CONFIG_SYS_DDR_TIMING_2_667 0x0fa074d1
71 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
72 #define CONFIG_SYS_DDR_MODE_1_667 0x00040852
73 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
74 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100
76 #define CONFIG_SYS_DDR_TIMING_3_800 0x00040000
77 #define CONFIG_SYS_DDR_TIMING_0_800 0x00770802
78 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543
79 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1
80 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
81 #define CONFIG_SYS_DDR_MODE_1_800 0x00040852
82 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
83 #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
85 fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
86 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
87 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
88 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
89 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_400,
90 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_400,
91 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_400,
92 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_400,
93 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
94 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
95 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_400,
96 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_400,
97 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
98 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_400,
99 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
100 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_400,
101 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
102 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
103 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
104 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
105 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
106 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
107 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
108 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
109 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
112 fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = {
113 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
114 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
115 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
116 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_533,
117 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_533,
118 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_533,
119 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_533,
120 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
121 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
122 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_533,
123 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_533,
124 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
125 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_533,
126 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
127 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_533,
128 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
129 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
130 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
131 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
132 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
133 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
134 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
135 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
136 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
139 fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
140 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
141 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
142 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
143 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
144 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
145 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
146 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
147 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
148 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
149 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
150 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
151 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
152 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
153 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
154 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
155 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
156 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
157 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
158 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
159 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
160 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
161 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
162 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
163 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
166 fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
167 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
168 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
169 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
170 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
171 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
172 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
173 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
174 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
175 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
176 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
177 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
178 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
179 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
180 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
181 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
182 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
183 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
184 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
185 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
186 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
187 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
188 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
189 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
190 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
194 * Fixed sdram init -- doesn't use serial presence detect.
197 phys_size_t fixed_sdram (void)
200 fsl_ddr_cfg_regs_t ddr_cfg_regs;
202 struct cpu_type *cpu;
203 ulong ddr_freq, ddr_freq_mhz;
206 /* P1020 and it's derivatives support max 32bit DDR width */
207 if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
208 cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
209 ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
211 ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
213 #if defined(CONFIG_SYS_RAMBOOT)
216 ddr_freq = get_ddr_freq(0);
217 ddr_freq_mhz = ddr_freq / 1000000;
219 printf("Configuring DDR for %s MT/s data rate\n",
220 strmhz(buf, ddr_freq));
222 if(ddr_freq_mhz <= 400)
223 memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
224 else if(ddr_freq_mhz <= 533)
225 memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
226 else if(ddr_freq_mhz <= 667)
227 memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
228 else if(ddr_freq_mhz <= 800)
229 memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
231 panic("Unsupported DDR data rate %s MT/s data rate\n",
232 strmhz(buf, ddr_freq));
234 /* P1020 and it's derivatives support max 32bit DDR width */
235 if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
236 cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
237 ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
238 ddr_cfg_regs.cs[0].bnds = 0x0000001F;
241 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
243 set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1);