2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
27 #include <asm/cache.h>
28 #include <asm/immap_85xx.h>
29 #include <asm/fsl_serdes.h>
33 #include <fdt_support.h>
40 DECLARE_GLOBAL_DATA_PTR;
42 #define VSC7385_RST_SET 0x00080000
43 #define SLIC_RST_SET 0x00040000
44 #define SGMII_PHY_RST_SET 0x00020000
45 #define PCIE_RST_SET 0x00010000
46 #define RGMII_PHY_RST_SET 0x02000000
48 #define USB_RST_CLR 0x04000000
50 #define GPIO_DIR 0x060f0000
52 #define BOARD_PERI_RST_SET VSC7385_RST_SET | SLIC_RST_SET | \
53 SGMII_PHY_RST_SET | PCIE_RST_SET | \
56 #define SYSCLK_MASK 0x00200000
57 #define BOARDREV_MASK 0x10100000
58 #define BOARDREV_C 0x00100000
59 #define BOARDREV_D 0x00000000
61 #define SYSCLK_66 66666666
62 #define SYSCLK_100 100000000
64 unsigned long get_board_sys_clk(ulong dummy)
66 volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
67 u32 val_gpdat, sysclk_gpio;
69 val_gpdat = in_be32(&pgpio->gpdat);
70 sysclk_gpio = val_gpdat & SYSCLK_MASK;
81 int board_early_init_f (void)
83 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
85 setbits_be32(&gur->pmuxcr,
86 (MPC85xx_PMUXCR_SDHC_CD |
87 MPC85xx_PMUXCR_SDHC_WP));
94 u32 val_gpdat, board_rev_gpio;
95 volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
99 val_gpdat = in_be32(&pgpio->gpdat);
100 board_rev_gpio = val_gpdat & BOARDREV_MASK;
101 if (board_rev_gpio == BOARDREV_C)
103 else if (board_rev_gpio == BOARDREV_D)
106 panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);
109 printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
110 setbits_be32(&pgpio->gpdir, GPIO_DIR);
113 * Bringing the following peripherals out of reset via GPIOs
114 * 0 = reset and 1 = out of reset
115 * GPIO12 - Reset to Ethernet Switch
116 * GPIO13 - Reset to SLIC/SLAC devices
117 * GPIO14 - Reset to SGMII_PHY_N
118 * GPIO15 - Reset to PCIe slots
119 * GPIO6 - Reset to RGMII PHY
120 * GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset
122 clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET);
127 int board_early_init_r(void)
129 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
130 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
131 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
132 unsigned int orig_bus = i2c_get_bus_num();
136 if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0,
137 1, &i2c_data, sizeof(i2c_data)) == 0) {
139 puts("NOR Flash Bank : Secondary\n");
141 puts("NOR Flash Bank : Primary\n");
143 if (i2c_data & 0x1) {
144 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
145 puts("SD/MMC : 8-bit Mode\n");
146 puts("eSPI : Disabled\n");
148 puts("SD/MMC : 4-bit Mode\n");
149 puts("eSPI : Enabled\n");
152 puts("Failed reading I2C Chip 0x18 on bus 1\n");
154 i2c_set_bus_num(orig_bus);
157 * Remap Boot flash region to caching-inhibited
158 * so that flash can be erased properly.
161 /* Flush d-cache and invalidate i-cache of any FLASH data */
165 /* invalidate existing TLB entry for flash */
166 disable_tlb(flash_esel);
168 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
169 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
170 0, flash_esel, BOOKE_PAGESZ_16M, 1);
176 #ifdef CONFIG_TSEC_ENET
177 int board_eth_init(bd_t *bis)
179 struct tsec_info_struct tsec_info[4];
182 unsigned int vscfw_addr;
185 SET_STD_TSEC_INFO(tsec_info[num], 1);
189 SET_STD_TSEC_INFO(tsec_info[num], 2);
193 SET_STD_TSEC_INFO(tsec_info[num], 3);
194 if (is_serdes_configured(SGMII_TSEC3)) {
195 puts("eTSEC3 is in sgmii mode.\n");
196 tsec_info[num].flags |= TSEC_SGMII;
201 printf("No TSECs initialized\n");
204 #ifdef CONFIG_VSC7385_ENET
205 /* If a VSC7385 microcode image is present, then upload it. */
206 if ((tmp = getenv ("vscfw_addr")) != NULL) {
207 vscfw_addr = simple_strtoul (tmp, NULL, 16);
208 printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
209 if (vsc7385_upload_firmware((void *) vscfw_addr,
210 CONFIG_VSC7385_IMAGE_SIZE))
211 puts("Failure uploading VSC7385 microcode.\n");
213 puts("No address specified for VSC7385 microcode.\n");
216 tsec_eth_init(bis, tsec_info, num);
218 return pci_eth_init(bis);
222 #if defined(CONFIG_OF_BOARD_SETUP)
223 extern void ft_pci_board_setup(void *blob);
225 void ft_board_setup(void *blob, bd_t *bd)
230 ft_cpu_setup(blob, bd);
232 base = getenv_bootm_low();
233 size = getenv_bootm_size();
235 #if defined(CONFIG_PCI)
236 ft_pci_board_setup(blob);
237 #endif /* #if defined(CONFIG_PCI) */
239 fdt_fixup_memory(blob, (u64)base, (u64)size);