2 * Copyright 2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/immap_85xx.h>
28 #include <asm/fsl_pci.h>
30 #include <fdt_support.h>
32 DECLARE_GLOBAL_DATA_PTR;
35 static struct pci_controller pcie1_hose;
39 static struct pci_controller pcie2_hose;
42 void pci_init_board(void)
44 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
45 struct fsl_pci_info pci_info[2];
46 u32 devdisr, pordevsr, io_sel, host_agent;
47 int first_free_busno = 0;
50 int pcie_ep, pcie_configured;
52 devdisr = in_be32(&gur->devdisr);
53 pordevsr = in_be32(&gur->pordevsr);
54 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
55 host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
57 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
58 devdisr, io_sel, host_agent);
60 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
61 printf (" eTSEC2 is in sgmii mode.\n");
65 pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
66 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
68 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
69 SET_STD_PCIE_INFO(pci_info[num], 2);
70 printf(" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
71 pcie_ep ? "End Point" : "Root Complex",
73 first_free_busno = fsl_pci_init_port(&pci_info[num++],
74 &pcie2_hose, first_free_busno);
76 printf (" PCIE2: disabled\n");
80 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
84 pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
85 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
87 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
88 SET_STD_PCIE_INFO(pci_info[num], 1);
89 printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
90 pcie_ep ? "End Point" : "Root Complex",
92 first_free_busno = fsl_pci_init_port(&pci_info[num++],
93 &pcie1_hose, first_free_busno);
95 printf (" PCIE1: disabled\n");
99 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
103 void ft_pci_board_setup(void *blob)
105 /* According to h/w manual, PCIE2 is at lower address(0x9000)
106 * than PCIE1(0xa000).
107 * Hence PCIE2 is made to occupy the pci1 position in dts to
108 * keep the addresses sorted there.
109 * Generally the case with all FSL SOCs.
112 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
115 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);