2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 struct fsl_e_tlb_entry tlb_table[] = {
11 /* TLB 0 - for temp stack in cache */
12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
13 CONFIG_SYS_INIT_RAM_ADDR_PHYS,
14 MAS3_SX|MAS3_SW|MAS3_SR, 0,
15 0, 0, BOOKE_PAGESZ_4K, 0),
16 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
17 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
18 MAS3_SX|MAS3_SW|MAS3_SR, 0,
19 0, 0, BOOKE_PAGESZ_4K, 0),
20 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
21 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
22 MAS3_SX|MAS3_SW|MAS3_SR, 0,
23 0, 0, BOOKE_PAGESZ_4K, 0),
24 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
25 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
26 MAS3_SX|MAS3_SW|MAS3_SR, 0,
27 0, 0, BOOKE_PAGESZ_4K, 0),
30 /* *I*** - Covers boot page */
31 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
32 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
33 0, 0, BOOKE_PAGESZ_4K, 1),
36 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
37 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
38 0, 1, BOOKE_PAGESZ_1M, 1),
40 #ifndef CONFIG_SPL_BUILD
41 /* W**G* - Flash/promjet, localbus */
42 /* This will be changed to *I*G* after relocation to RAM. */
43 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
44 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
45 0, 2, BOOKE_PAGESZ_16M, 1),
47 #if defined(CONFIG_PCI)
49 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
50 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
51 0, 3, BOOKE_PAGESZ_1G, 1),
54 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
55 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
56 0, 4, BOOKE_PAGESZ_256K, 1),
58 #endif /* #if defined(CONFIG_PCI) */
61 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
62 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
63 0, 5, BOOKE_PAGESZ_1M, 1),
65 /* *I*G - VSC7385 Switch */
66 SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
67 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
68 0, 6, BOOKE_PAGESZ_1M, 1),
70 #ifdef CONFIG_SYS_INIT_L2_ADDR
72 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
73 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
74 0, 11, BOOKE_PAGESZ_256K, 1),
75 #if CONFIG_SYS_L2_SIZE >= (256 << 10)
76 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
77 CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
78 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
79 0, 12, BOOKE_PAGESZ_256K, 1),
83 #if defined(CONFIG_SYS_RAMBOOT) || \
84 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
85 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
86 MAS3_SX|MAS3_SW|MAS3_SR, 0,
87 0, 7, BOOKE_PAGESZ_1G, 1)
91 int num_tlb_entries = ARRAY_SIZE(tlb_table);