git.sur5r.net Git - u-boot/blob - board/freescale/p2020come/tlb.c

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/mmu.h>
  25
  26 struct fsl_e_tlb_entry tlb_table[] = {
  27         /* TLB 0 - for temp stack in cache */
  28         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  29                         CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  30                         MAS3_SW|MAS3_SR, 0,
  31                         0, 0, BOOKE_PAGESZ_4K, 0),
  32         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
  33                         CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  34                         MAS3_SW|MAS3_SR, 0,
  35                         0, 0, BOOKE_PAGESZ_4K, 0),
  36         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
  37                         CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  38                         MAS3_SW|MAS3_SR, 0,
  39                         0, 0, BOOKE_PAGESZ_4K, 0),
  40         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
  41                         CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  42                         MAS3_SW|MAS3_SR, 0,
  43                         0, 0, BOOKE_PAGESZ_4K, 0),
  44
  45         /* TLB 1 */
  46         /* *I*** - Covers boot page */
  47         SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  48                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  49                         0, 0, BOOKE_PAGESZ_4K, 1),
  50
  51         /* *I*G* - CCSRBAR */
  52         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  53                         MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  54                         0, 1, BOOKE_PAGESZ_1M, 1),
  55
  56 #if defined(CONFIG_PCI)
  57         /* *I*G* - PCI3 - PCI2 0x8000,0000 - 0xbfff,ffff, size = 1G */
  58         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
  59                         MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  60                         0, 2, BOOKE_PAGESZ_1G, 1),
  61
  62         /* *I*G* - PCI1 0xC000,0000 - 0xcfff,ffff, size = 256M */
  63         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_VIRT,
  64                         MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  65                         0, 3, BOOKE_PAGESZ_256M, 1),
  66
  67         /* *I*G* - PCI1  0xD000,0000 - 0xDFFF,FFFF, size = 256M */
  68         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
  69                         CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
  70                         MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  71                         0, 4, BOOKE_PAGESZ_256M, 1),
  72
  73         /*
  74          * *I*G* - PCI I/O
  75          *
  76          * PCI3 => 0xFFC10000
  77          * PCI2 => 0xFFC2,0000
  78          * PCI1 => 0xFFC3,0000
  79          */
  80         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
  81                         MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  82                         0, 5, BOOKE_PAGESZ_256K, 1),
  83 #endif /* #if defined(CONFIG_PCI) */
  84
  85 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
  86         /* *I*G - DDR3  2G     Part 1: 0 - 0x3fff,ffff , size = 1G */
  87         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
  88                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  89                         0, 6, BOOKE_PAGESZ_256K, 1),
  90
  91         /*        DDR3  2G     Part 2: 0x4000,0000 - 0x7fff,ffff , size = 1G */
  92         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
  93                         CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
  94                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  95                         0, 7, BOOKE_PAGESZ_256K, 1),
  96 #endif
  97 };
  98
  99 int num_tlb_entries = ARRAY_SIZE(tlb_table);