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powerpc/85xx: Add networking support to P1023RDS
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1 /*
2  * Copyright 2008-2009 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * Version 2 as published by the Free Software Foundation.
7  */
8
9 #include <common.h>
10
11 #include <asm/fsl_ddr_sdram.h>
12 #include <asm/fsl_ddr_dimm_params.h>
13
14 typedef struct {
15         u32 datarate_mhz_low;
16         u32 datarate_mhz_high;
17         u32 n_ranks;
18         u32 clk_adjust;
19         u32 cpo;
20         u32 write_data_delay;
21         u32 force_2T;
22 } board_specific_parameters_t;
23
24 /* ranges for parameters:
25  *  wr_data_delay = 0-6
26  *  clk adjust = 0-8
27  *  cpo 2-0x1E (30)
28  */
29
30 const board_specific_parameters_t board_specific_parameters[][20] = {
31         {
32         /*      memory controller 0                     */
33         /*        lo|  hi|  num|  clk| cpo|wrdata|2T    */
34         /*       mhz| mhz|ranks|adjst|    | delay|      */
35 #ifdef CONFIG_FSL_DDR2
36                 {  0, 333,    2,    4,   0x1f,    2,  0},
37                 {334, 400,    2,    4,   0x1f,    2,  0},
38                 {401, 549,    2,    4,   0x1f,    2,  0},
39                 {550, 680,    2,    4,   0x1f,    3,  0},
40                 {681, 850,    2,    4,   0x1f,    4,  0},
41                 {  0, 333,    1,    4,   0x1f,    2,  0},
42                 {334, 400,    1,    4,   0x1f,    2,  0},
43                 {401, 549,    1,    4,   0x1f,    2,  0},
44                 {550, 680,    1,    4,   0x1f,    3,  0},
45                 {681, 850,    1,    4,   0x1f,    4,  0}
46 #else
47                 {  0, 850,    2,    6,   0x1f,    4,  0},
48                 {  0, 850,    1,    4,   0x1f,    4,  0}
49 #endif
50         },
51 };
52
53 void fsl_ddr_board_options(memctl_options_t *popts,
54                                 dimm_params_t *pdimm,
55                                 unsigned int ctrl_num)
56 {
57         const board_specific_parameters_t *pbsp =
58                                 &(board_specific_parameters[ctrl_num][0]);
59         u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
60                                 sizeof(board_specific_parameters[0][0]);
61         u32 i;
62         ulong ddr_freq;
63
64         /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
65          * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
66          * there are two dimms in the controller, set odt_rd_cfg to 3 and
67          * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
68          */
69         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
70                         popts->cs_local_opts[i].odt_rd_cfg = 0;
71                         popts->cs_local_opts[i].odt_wr_cfg = 1;
72         }
73
74         /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
75          * freqency and n_banks specified in board_specific_parameters table.
76          */
77         ddr_freq = get_ddr_freq(0) / 1000000;
78         for (i = 0; i < num_params; i++) {
79                 if (ddr_freq >= pbsp->datarate_mhz_low &&
80                     ddr_freq <= pbsp->datarate_mhz_high &&
81                     pdimm->n_ranks == pbsp->n_ranks) {
82                         popts->clk_adjust = pbsp->clk_adjust;
83                         popts->cpo_override = pbsp->cpo;
84                         popts->write_data_delay = pbsp->write_data_delay;
85                         popts->twoT_en = pbsp->force_2T;
86                         break;
87                 }
88                 pbsp++;
89         }
90
91         if (i == num_params) {
92                 printf("Warning: board specific timing not found "
93                         "for data rate %lu MT/s!\n", ddr_freq);
94         }
95
96         /*
97          * Factors to consider for half-strength driver enable:
98          *      - number of DIMMs installed
99          */
100         popts->half_strength_driver_enable = 0;
101         popts->wrlvl_en = 1;
102         /* Write leveling override */
103         popts->wrlvl_override = 1;
104         popts->wrlvl_sample = 0xa;
105         popts->wrlvl_start = 0x8;
106         /* Rtt and Rtt_WR override */
107         popts->rtt_override = 1;
108         popts->rtt_override_value = DDR3_RTT_120_OHM;
109         popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
110 }