git.sur5r.net Git - u-boot/blob - board/freescale/p2020ds/ddr.c

   1 /*
   2  * Copyright 2008-2009 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10
  11 #include <asm/fsl_ddr_sdram.h>
  12 #include <asm/fsl_ddr_dimm_params.h>
  13
  14 struct board_specific_parameters {
  15         u32 n_ranks;
  16         u32 datarate_mhz_high;
  17         u32 clk_adjust;
  18         u32 cpo;
  19         u32 write_data_delay;
  20         u32 force_2T;
  21 };
  22
  23
  24 /*
  25  * This table contains all valid speeds we want to override with board
  26  * specific parameters. datarate_mhz_high values need to be in ascending order
  27  * for each n_ranks group.
  28  *
  29  * ranges for parameters:
  30  *  wr_data_delay = 0-6
  31  *  clk adjust = 0-8
  32  *  cpo 2-0x1E (30)
  33  */
  34 static const struct board_specific_parameters dimm0[] = {
  35         /*
  36          * memory controller 0
  37          *   num|  hi|  clk| cpo|wrdata|2T
  38          * ranks| mhz|adjst|    | delay|
  39          */
  40 #ifdef CONFIG_FSL_DDR2
  41         {2,  549,    4,   0x1f,    2,  0},
  42         {2,  680,    4,   0x1f,    3,  0},
  43         {2,  850,    4,   0x1f,    4,  0},
  44         {1,  549,    4,   0x1f,    2,  0},
  45         {1,  680,    4,   0x1f,    3,  0},
  46         {1,  850,    4,   0x1f,    4,  0},
  47 #else
  48         {2,  850,    6,   0x1f,    4,  0},
  49         {1,  850,    4,   0x1f,    4,  0},
  50 #endif
  51         {}
  52 };
  53
  54 void fsl_ddr_board_options(memctl_options_t *popts,
  55                                 dimm_params_t *pdimm,
  56                                 unsigned int ctrl_num)
  57 {
  58         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  59         ulong ddr_freq;
  60
  61         if (ctrl_num) {
  62                 printf("Wrong parameter for controller number %d", ctrl_num);
  63                 return;
  64         }
  65         if (!pdimm->n_ranks)
  66                 return;
  67
  68         pbsp = dimm0;
  69
  70         /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  71          * freqency and n_banks specified in board_specific_parameters table.
  72          */
  73         ddr_freq = get_ddr_freq(0) / 1000000;
  74         while (pbsp->datarate_mhz_high) {
  75                 if (pbsp->n_ranks == pdimm->n_ranks) {
  76                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  77                                 popts->clk_adjust = pbsp->clk_adjust;
  78                                 popts->cpo_override = pbsp->cpo;
  79                                 popts->write_data_delay =
  80                                         pbsp->write_data_delay;
  81                                 popts->twoT_en = pbsp->force_2T;
  82                                 goto found;
  83                         }
  84                         pbsp_highest = pbsp;
  85                 }
  86                 pbsp++;
  87         }
  88
  89         if (pbsp_highest) {
  90                 printf("Error: board specific timing not found "
  91                         "for data rate %lu MT/s!\n"
  92                         "Trying to use the highest speed (%u) parameters\n",
  93                         ddr_freq, pbsp_highest->datarate_mhz_high);
  94                 popts->clk_adjust = pbsp_highest->clk_adjust;
  95                 popts->cpo_override = pbsp_highest->cpo;
  96                 popts->write_data_delay = pbsp_highest->write_data_delay;
  97                 popts->twoT_en = pbsp_highest->force_2T;
  98         } else {
  99                 panic("DIMM is not supported by this board");
 100         }
 101
 102 found:
 103         /*
 104          * Factors to consider for half-strength driver enable:
 105          *      - number of DIMMs installed
 106          */
 107         popts->half_strength_driver_enable = 0;
 108         popts->wrlvl_en = 1;
 109         /* Write leveling override */
 110         popts->wrlvl_override = 1;
 111         popts->wrlvl_sample = 0xa;
 112         popts->wrlvl_start = 0x8;
 113         /* Rtt and Rtt_WR override */
 114         popts->rtt_override = 1;
 115         popts->rtt_override_value = DDR3_RTT_120_OHM;
 116         popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
 117 }