2 * Copyright 2007-2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
35 #include <fdt_support.h>
37 #include <asm/fsl_law.h>
41 #include "../common/ngpixis.h"
42 #include "../common/sgmii_riser.h"
44 DECLARE_GLOBAL_DATA_PTR;
46 phys_size_t fixed_sdram(void);
52 puts("Board: P2020DS ");
53 #ifdef CONFIG_PHYS_64BIT
54 puts("(36-bit addrmap) ");
57 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
58 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
60 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
61 sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
64 /* The lower two bits are the actual vbank number */
65 printf("vBank: %d\n", sw & 3);
72 const char *board_hwconfig = "foo:bar=baz";
73 const char *cpu_hwconfig = "foo:bar=baz";
75 phys_size_t initdram(int board_type)
77 phys_size_t dram_size = 0;
79 puts("Initializing....");
82 dram_size = fsl_ddr_sdram();
84 dram_size = fixed_sdram();
86 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
88 LAW_TRGT_IF_DDR) < 0) {
89 printf("ERROR setting Local Access Windows for DDR\n");
93 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
94 dram_size *= 0x100000;
100 #if !defined(CONFIG_DDR_SPD)
102 * Fixed sdram init -- doesn't use serial presence detect.
105 phys_size_t fixed_sdram(void)
107 volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
110 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
111 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
112 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
113 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
114 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
115 ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
116 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
117 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
118 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
119 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
120 ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
121 ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
122 ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
123 ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
124 ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
126 if (!strcmp("performance", getenv("perf_mode"))) {
127 /* Performance Mode Values */
129 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
130 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
131 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
132 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
133 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
139 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
141 /* Stable Mode Values */
143 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
144 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
145 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
146 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
147 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
149 /* ECC will be assumed in stable mode */
150 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
151 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
152 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
158 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
161 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
163 debug("DDR - 1st controller: memory initializing\n");
165 * Poll until memory is initialized.
166 * 512 Meg at 400 might hit this 200 times or so.
168 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
170 debug("DDR: memory initialized\n\n");
175 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
181 static struct pci_controller pcie1_hose;
185 static struct pci_controller pcie2_hose;
189 static struct pci_controller pcie3_hose;
193 void pci_init_board(void)
195 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
196 struct fsl_pci_info pci_info[3];
197 u32 devdisr, pordevsr, io_sel;
198 int first_free_busno = 0;
201 int pcie_ep, pcie_configured;
203 devdisr = in_be32(&gur->devdisr);
204 pordevsr = in_be32(&gur->pordevsr);
205 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
207 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
209 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
210 printf("eTSEC2 is in sgmii mode.\n");
211 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
212 printf("eTSEC3 is in sgmii mode.\n");
216 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
218 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
219 SET_STD_PCIE_INFO(pci_info[num], 2);
220 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
221 printf("PCIE2: connected to ULI as %s (base addr %lx)\n",
222 pcie_ep ? "Endpoint" : "Root Complex",
224 first_free_busno = fsl_pci_init_port(&pci_info[num++],
225 &pcie2_hose, first_free_busno);
228 * The workaround doesn't work on p2020 because the location
229 * we try and read isn't valid on p2020, fix this later
233 * Activate ULI1575 legacy chip by performing a fake
234 * memory access. Needed to make ULI RTC work.
235 * Device 1d has the first on-board memory BAR.
238 pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0),
239 PCI_BASE_ADDRESS_1, &temp32);
240 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
241 void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
243 debug(" uli1575 read to %p\n", p);
248 printf("PCIE2: disabled\n");
252 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
256 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
258 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
259 SET_STD_PCIE_INFO(pci_info[num], 3);
260 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
261 printf("PCIE3: connected to Slot 1 as %s (base addr %lx)\n",
262 pcie_ep ? "Endpoint" : "Root Complex",
264 first_free_busno = fsl_pci_init_port(&pci_info[num++],
265 &pcie3_hose, first_free_busno);
267 printf("PCIE3: disabled\n");
271 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
275 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
277 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
278 SET_STD_PCIE_INFO(pci_info[num], 1);
279 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
280 printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
281 pcie_ep ? "Endpoint" : "Root Complex",
283 first_free_busno = fsl_pci_init_port(&pci_info[num++],
284 &pcie1_hose, first_free_busno);
286 printf("PCIE1: disabled\n");
290 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
295 int board_early_init_r(void)
297 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
298 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
301 * Remap Boot flash + PROMJET region to caching-inhibited
302 * so that flash can be erased properly.
305 /* Flush d-cache and invalidate i-cache of any FLASH data */
309 /* invalidate existing TLB entry for flash + promjet */
310 disable_tlb(flash_esel);
312 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
313 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
314 0, flash_esel, BOOKE_PAGESZ_256M, 1);
319 #ifdef CONFIG_TSEC_ENET
320 int board_eth_init(bd_t *bis)
322 struct tsec_info_struct tsec_info[4];
323 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
327 SET_STD_TSEC_INFO(tsec_info[num], 1);
331 SET_STD_TSEC_INFO(tsec_info[num], 2);
332 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
333 tsec_info[num].flags |= TSEC_SGMII;
337 SET_STD_TSEC_INFO(tsec_info[num], 3);
338 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
339 tsec_info[num].flags |= TSEC_SGMII;
344 printf("No TSECs initialized\n");
349 #ifdef CONFIG_FSL_SGMII_RISER
350 fsl_sgmii_riser_init(tsec_info, num);
353 tsec_eth_init(bis, tsec_info, num);
355 return pci_eth_init(bis);
359 #if defined(CONFIG_OF_BOARD_SETUP)
360 void ft_board_setup(void *blob, bd_t *bd)
365 ft_cpu_setup(blob, bd);
367 base = getenv_bootm_low();
368 size = getenv_bootm_size();
370 fdt_fixup_memory(blob, (u64)base, (u64)size);
374 #ifdef CONFIG_FSL_SGMII_RISER
375 fsl_sgmii_riser_fdt_fixup(blob);
381 void board_lmb_reserve(struct lmb *lmb)
383 cpu_mp_lmb_reserve(lmb);