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powerpc/85xx: Add networking support to P1023RDS
[u-boot] / board / freescale / p2020ds / p2020ds.c
1 /*
2  * Copyright 2007-2011 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22
23 #include <common.h>
24 #include <command.h>
25 #include <pci.h>
26 #include <asm/processor.h>
27 #include <asm/mmu.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
32 #include <asm/io.h>
33 #include <asm/fsl_serdes.h>
34 #include <miiphy.h>
35 #include <libfdt.h>
36 #include <fdt_support.h>
37 #include <fsl_mdio.h>
38 #include <tsec.h>
39 #include <asm/fsl_law.h>
40 #include <netdev.h>
41
42 #include "../common/ngpixis.h"
43 #include "../common/sgmii_riser.h"
44
45 DECLARE_GLOBAL_DATA_PTR;
46
47 int board_early_init_f(void)
48 {
49 #ifdef CONFIG_MMC
50         ccsr_gur_t *gur = (ccsr_gur_t *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
51
52         setbits_be32(&gur->pmuxcr,
53                          (MPC85xx_PMUXCR_SDHC_CD |
54                          MPC85xx_PMUXCR_SDHC_WP));
55 #endif
56
57         return 0;
58 }
59
60 int checkboard(void)
61 {
62         u8 sw;
63
64         puts("Board: P2020DS ");
65 #ifdef CONFIG_PHYS_64BIT
66         puts("(36-bit addrmap) ");
67 #endif
68
69         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
70                 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
71
72         sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
73         sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
74
75         if (sw < 0x8)
76                 /* The lower two bits are the actual vbank number */
77                 printf("vBank: %d\n", sw & 3);
78         else
79                 puts("Promjet\n");
80
81         return 0;
82 }
83
84 #if !defined(CONFIG_DDR_SPD)
85 /*
86  * Fixed sdram init -- doesn't use serial presence detect.
87  */
88
89 phys_size_t fixed_sdram(void)
90 {
91         volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
92         uint d_init;
93
94         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
95         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
96         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
97         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
98         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
99         ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
100         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
101         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
102         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
103         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
104         ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
105         ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
106         ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
107         ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
108         ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
109
110         if (!strcmp("performance", getenv("perf_mode"))) {
111                 /* Performance Mode Values */
112
113                 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
114                 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
115                 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
116                 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
117                 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
118
119                 asm("sync;isync");
120
121                 udelay(500);
122
123                 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
124         } else {
125                 /* Stable Mode Values */
126
127                 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
128                 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
129                 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
130                 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
131                 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
132
133                 /* ECC will be assumed in stable mode */
134                 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
135                 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
136                 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
137
138                 asm("sync;isync");
139
140                 udelay(500);
141
142                 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
143         }
144
145 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
146         d_init = 1;
147         debug("DDR - 1st controller: memory initializing\n");
148         /*
149          * Poll until memory is initialized.
150          * 512 Meg at 400 might hit this 200 times or so.
151          */
152         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
153                 udelay(1000);
154         debug("DDR: memory initialized\n\n");
155         asm("sync; isync");
156         udelay(500);
157 #endif
158
159         if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
160                          CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,
161                          LAW_TRGT_IF_DDR) < 0) {
162                 printf("ERROR setting Local Access Windows for DDR\n");
163                 return 0;
164         };
165
166         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
167 }
168
169 #endif
170
171 #ifdef CONFIG_PCI
172 void pci_init_board(void)
173 {
174         fsl_pcie_init_board(0);
175 }
176 #endif
177
178 int board_early_init_r(void)
179 {
180         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
181         const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
182
183         /*
184          * Remap Boot flash + PROMJET region to caching-inhibited
185          * so that flash can be erased properly.
186          */
187
188         /* Flush d-cache and invalidate i-cache of any FLASH data */
189         flush_dcache();
190         invalidate_icache();
191
192         /* invalidate existing TLB entry for flash + promjet */
193         disable_tlb(flash_esel);
194
195         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
196                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
197                         0, flash_esel, BOOKE_PAGESZ_256M, 1);
198
199         return 0;
200 }
201
202 #ifdef CONFIG_TSEC_ENET
203 int board_eth_init(bd_t *bis)
204 {
205         struct fsl_pq_mdio_info mdio_info;
206         struct tsec_info_struct tsec_info[4];
207         int num = 0;
208
209 #ifdef CONFIG_TSEC1
210         SET_STD_TSEC_INFO(tsec_info[num], 1);
211         num++;
212 #endif
213 #ifdef CONFIG_TSEC2
214         SET_STD_TSEC_INFO(tsec_info[num], 2);
215         if (is_serdes_configured(SGMII_TSEC2)) {
216                 puts("eTSEC2 is in sgmii mode.\n");
217                 tsec_info[num].flags |= TSEC_SGMII;
218         }
219         num++;
220 #endif
221 #ifdef CONFIG_TSEC3
222         SET_STD_TSEC_INFO(tsec_info[num], 3);
223         if (is_serdes_configured(SGMII_TSEC3)) {
224                 puts("eTSEC3 is in sgmii mode.\n");
225                 tsec_info[num].flags |= TSEC_SGMII;
226 }
227         num++;
228 #endif
229
230         if (!num) {
231                 printf("No TSECs initialized\n");
232
233                 return 0;
234         }
235
236 #ifdef CONFIG_FSL_SGMII_RISER
237         fsl_sgmii_riser_init(tsec_info, num);
238 #endif
239
240         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
241         mdio_info.name = DEFAULT_MII_NAME;
242
243         fsl_pq_mdio_init(bis, &mdio_info);
244
245         tsec_eth_init(bis, tsec_info, num);
246
247         return pci_eth_init(bis);
248 }
249 #endif
250
251 #if defined(CONFIG_OF_BOARD_SETUP)
252 void ft_board_setup(void *blob, bd_t *bd)
253 {
254         phys_addr_t base;
255         phys_size_t size;
256
257         ft_cpu_setup(blob, bd);
258
259         base = getenv_bootm_low();
260         size = getenv_bootm_size();
261
262         fdt_fixup_memory(blob, (u64)base, (u64)size);
263
264         FT_FSL_PCI_SETUP;
265
266 #ifdef CONFIG_FSL_SGMII_RISER
267         fsl_sgmii_riser_fdt_fixup(blob);
268 #endif
269 }
270 #endif