git.sur5r.net Git - u-boot/blob - board/freescale/p2020ds/p2020ds.c

   1 /*
   2  * Copyright 2007-2009 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/mmu.h>
  28 #include <asm/cache.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/fsl_pci.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <asm/io.h>
  33 #include <miiphy.h>
  34 #include <libfdt.h>
  35 #include <fdt_support.h>
  36 #include <tsec.h>
  37 #include <asm/fsl_law.h>
  38 #include <asm/mp.h>
  39 #include <netdev.h>
  40
  41 #include "../common/pixis.h"
  42 #include "../common/sgmii_riser.h"
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 phys_size_t fixed_sdram(void);
  47
  48 int checkboard(void)
  49 {
  50         u8 sw7;
  51         u8 *pixis_base = (u8 *)PIXIS_BASE;
  52
  53         puts("Board: P2020DS ");
  54 #ifdef CONFIG_PHYS_64BIT
  55         puts("(36-bit addrmap) ");
  56 #endif
  57
  58         printf("Sys ID: 0x%02x, "
  59                 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  60                 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  61                 in_8(pixis_base + PIXIS_PVER));
  62
  63         sw7 = in_8(pixis_base + PIXIS_SW(7));
  64         switch ((sw7 & PIXIS_SW7_LBMAP) >> 6) {
  65                 case 0:
  66                 case 1:
  67                         printf ("vBank: %d\n", ((sw7 & PIXIS_SW7_VBANK) >> 4));
  68                         break;
  69                 case 2:
  70                 case 3:
  71                         puts ("Promjet\n");
  72                         break;
  73         }
  74
  75         return 0;
  76 }
  77
  78 phys_size_t initdram(int board_type)
  79 {
  80         phys_size_t dram_size = 0;
  81
  82         puts("Initializing....");
  83
  84 #ifdef CONFIG_SPD_EEPROM
  85         dram_size = fsl_ddr_sdram();
  86 #else
  87         dram_size = fixed_sdram();
  88
  89         if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
  90                          dram_size,
  91                          LAW_TRGT_IF_DDR) < 0) {
  92                 printf("ERROR setting Local Access Windows for DDR\n");
  93                 return 0;
  94         };
  95 #endif
  96         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  97         dram_size *= 0x100000;
  98
  99         puts("    DDR: ");
 100         return dram_size;
 101 }
 102
 103 #if !defined(CONFIG_SPD_EEPROM)
 104 /*
 105  * Fixed sdram init -- doesn't use serial presence detect.
 106  */
 107
 108 phys_size_t fixed_sdram(void)
 109 {
 110         volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
 111         uint d_init;
 112
 113         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
 114         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
 115         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 116         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
 117         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
 118         ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
 119         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 120         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
 121         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
 122         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 123         ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
 124         ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
 125         ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
 126         ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
 127         ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
 128
 129         if (!strcmp("performance", getenv("perf_mode"))) {
 130                 /* Performance Mode Values */
 131
 132                 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
 133                 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
 134                 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
 135                 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
 136                 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
 137
 138                 asm("sync;isync");
 139
 140                 udelay(500);
 141
 142                 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
 143         } else {
 144                 /* Stable Mode Values */
 145
 146                 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
 147                 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 148                 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
 149                 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 150                 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 151
 152                 /* ECC will be assumed in stable mode */
 153                 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
 154                 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
 155                 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
 156
 157                 asm("sync;isync");
 158
 159                 udelay(500);
 160
 161                 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 162         }
 163
 164 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 165         d_init = 1;
 166         debug("DDR - 1st controller: memory initializing\n");
 167         /*
 168          * Poll until memory is initialized.
 169          * 512 Meg at 400 might hit this 200 times or so.
 170          */
 171         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
 172                 udelay(1000);
 173         debug("DDR: memory initialized\n\n");
 174         asm("sync; isync");
 175         udelay(500);
 176 #endif
 177
 178         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 179 }
 180
 181 #endif
 182
 183 #ifdef CONFIG_PCIE1
 184 static struct pci_controller pcie1_hose;
 185 #endif
 186
 187 #ifdef CONFIG_PCIE2
 188 static struct pci_controller pcie2_hose;
 189 #endif
 190
 191 #ifdef CONFIG_PCIE3
 192 static struct pci_controller pcie3_hose;
 193 #endif
 194
 195 int first_free_busno = 0;
 196
 197 #ifdef CONFIG_PCI
 198 void pci_init_board(void)
 199 {
 200         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 201         uint devdisr = gur->devdisr;
 202         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 203         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 204
 205         volatile ccsr_fsl_pci_t *pci;
 206         struct pci_controller *hose;
 207         int pcie_ep, pcie_configured;
 208         struct pci_region *r;
 209 /*              u32 temp32; */
 210
 211         debug("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 212                         devdisr, io_sel, host_agent);
 213
 214         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 215                 printf("    eTSEC2 is in sgmii mode.\n");
 216         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 217                 printf("    eTSEC3 is in sgmii mode.\n");
 218
 219 #ifdef CONFIG_PCIE2
 220         pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
 221         hose = &pcie2_hose;
 222         pcie_ep = (host_agent == 2) || (host_agent == 4) ||
 223                   (host_agent == 6) || (host_agent == 0);
 224         pcie_configured = (io_sel == 0x2) || (io_sel == 0xe);
 225         r = hose->regions;
 226
 227         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
 228                 printf("\n    PCIE2 connected to ULI as %s (base addr %x)",
 229                                 pcie_ep ? "End Point" : "Root Complex",
 230                                 (uint)pci);
 231                 if (pci->pme_msg_det) {
 232                         pci->pme_msg_det = 0xffffffff;
 233                         debug(" with errors.  Clearing.  Now 0x%08x",
 234                                 pci->pme_msg_det);
 235                 }
 236                 printf("\n");
 237
 238                 /* inbound */
 239                 r += fsl_pci_setup_inbound_windows(r);
 240
 241                 /* outbound memory */
 242                 pci_set_region(r++,
 243                                 CONFIG_SYS_PCIE2_MEM_BUS,
 244                                 CONFIG_SYS_PCIE2_MEM_PHYS,
 245                                 CONFIG_SYS_PCIE2_MEM_SIZE,
 246                                 PCI_REGION_MEM);
 247
 248                 /* outbound io */
 249                 pci_set_region(r++,
 250                                 CONFIG_SYS_PCIE2_IO_BUS,
 251                                 CONFIG_SYS_PCIE2_IO_PHYS,
 252                                 CONFIG_SYS_PCIE2_IO_SIZE,
 253                                 PCI_REGION_IO);
 254
 255                 hose->region_count = r - hose->regions;
 256                 hose->first_busno = first_free_busno;
 257                 pci_setup_indirect(hose, (int)&pci->cfg_addr,
 258                                   (int)&pci->cfg_data);
 259
 260                 fsl_pci_init(hose);
 261                 first_free_busno = hose->last_busno+1;
 262                 printf("    PCIE2 on bus %02x - %02x\n",
 263                         hose->first_busno, hose->last_busno);
 264
 265                 /*
 266                  * The workaround doesn't work on p2020 because the location
 267                  * we try and read isn't valid on p2020, fix this later
 268                  */
 269 #if 0
 270                 /*
 271                  * Activate ULI1575 legacy chip by performing a fake
 272                  * memory access.  Needed to make ULI RTC work.
 273                  * Device 1d has the first on-board memory BAR.
 274                  */
 275
 276                 pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0),
 277                                 PCI_BASE_ADDRESS_1, &temp32);
 278                 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
 279                         void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
 280                                                         temp32, 4, 0);
 281                         debug(" uli1575 read to %p\n", p);
 282                         in_be32(p);
 283                 }
 284 #endif
 285         } else {
 286                 printf("    PCIE2: disabled\n");
 287         }
 288 #else
 289         gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
 290 #endif
 291
 292 #ifdef CONFIG_PCIE3
 293         pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
 294         hose = &pcie3_hose;
 295         pcie_ep = (host_agent == 0) || (host_agent == 3) ||
 296                 (host_agent == 5) || (host_agent == 6);
 297         pcie_configured = (io_sel == 0x2) || (io_sel == 0x4);
 298         r = hose->regions;
 299
 300         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
 301                 printf("\n    PCIE3 connected to Slot 1 as %s (base addr %x)",
 302                                 pcie_ep ? "End Point" : "Root Complex",
 303                                 (uint)pci);
 304                 if (pci->pme_msg_det) {
 305                         pci->pme_msg_det = 0xffffffff;
 306                         debug(" with errors.  Clearing.  Now 0x%08x",
 307                                 pci->pme_msg_det);
 308                 }
 309                 printf("\n");
 310
 311                 /* inbound */
 312                 r += fsl_pci_setup_inbound_windows(r);
 313
 314                 /* outbound memory */
 315                 pci_set_region(r++,
 316                                 CONFIG_SYS_PCIE3_MEM_BUS,
 317                                 CONFIG_SYS_PCIE3_MEM_PHYS,
 318                                 CONFIG_SYS_PCIE3_MEM_SIZE,
 319                                 PCI_REGION_MEM);
 320
 321                 /* outbound io */
 322                 pci_set_region(r++,
 323                                 CONFIG_SYS_PCIE3_IO_BUS,
 324                                 CONFIG_SYS_PCIE3_IO_PHYS,
 325                                 CONFIG_SYS_PCIE3_IO_SIZE,
 326                                 PCI_REGION_IO);
 327
 328                 hose->region_count = r - hose->regions;
 329                 hose->first_busno = first_free_busno;
 330                 pci_setup_indirect(hose, (int)&pci->cfg_addr,
 331                                   (int)&pci->cfg_data);
 332
 333                 fsl_pci_init(hose);
 334
 335                 first_free_busno = hose->last_busno+1;
 336                 printf("    PCIE3 on bus %02x - %02x\n",
 337                                 hose->first_busno, hose->last_busno);
 338
 339         } else {
 340                 printf("    PCIE3: disabled\n");
 341         }
 342 #else
 343         gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
 344 #endif
 345
 346 #ifdef CONFIG_PCIE1
 347         pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 348         hose = &pcie1_hose;
 349         pcie_ep = (host_agent <= 1) || (host_agent == 4) || (host_agent == 5);
 350         pcie_configured  = (io_sel & 6) || (io_sel == 0xE) || (io_sel == 0xF);
 351         r = hose->regions;
 352
 353         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
 354                 printf("\n    PCIE1 connected to Slot 2 as %s (base addr %x)",
 355                                 pcie_ep ? "End Point" : "Root Complex",
 356                                 (uint)pci);
 357                 if (pci->pme_msg_det) {
 358                         pci->pme_msg_det = 0xffffffff;
 359                         debug(" with errors.  Clearing.  Now 0x%08x",
 360                                 pci->pme_msg_det);
 361                 }
 362                 printf("\n");
 363
 364                 /* inbound */
 365                 r += fsl_pci_setup_inbound_windows(r);
 366
 367                 /* outbound memory */
 368                 pci_set_region(r++,
 369                                 CONFIG_SYS_PCIE1_MEM_BUS,
 370                                 CONFIG_SYS_PCIE1_MEM_PHYS,
 371                                 CONFIG_SYS_PCIE1_MEM_SIZE,
 372                                 PCI_REGION_MEM);
 373
 374                 /* outbound io */
 375                 pci_set_region(r++,
 376                                 CONFIG_SYS_PCIE1_IO_BUS,
 377                                 CONFIG_SYS_PCIE1_IO_PHYS,
 378                                 CONFIG_SYS_PCIE1_IO_SIZE,
 379                                 PCI_REGION_IO);
 380
 381                 hose->region_count = r - hose->regions;
 382                 hose->first_busno = first_free_busno;
 383
 384                 pci_setup_indirect(hose, (int)&pci->cfg_addr,
 385                                   (int)&pci->cfg_data);
 386
 387                 fsl_pci_init(hose);
 388
 389                 first_free_busno = hose->last_busno+1;
 390                 printf("    PCIE1 on bus %02x - %02x\n",
 391                         hose->first_busno, hose->last_busno);
 392
 393         } else {
 394                 printf("    PCIE1: disabled\n");
 395         }
 396 #else
 397         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 398 #endif
 399 }
 400 #endif
 401
 402 int board_early_init_r(void)
 403 {
 404         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 405         const u8 flash_esel = 2;
 406
 407         /*
 408          * Remap Boot flash + PROMJET region to caching-inhibited
 409          * so that flash can be erased properly.
 410          */
 411
 412         /* Flush d-cache and invalidate i-cache of any FLASH data */
 413         flush_dcache();
 414         invalidate_icache();
 415
 416         /* invalidate existing TLB entry for flash + promjet */
 417         disable_tlb(flash_esel);
 418
 419         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 420                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 421                         0, flash_esel, BOOKE_PAGESZ_256M, 1);
 422
 423         return 0;
 424 }
 425
 426 #ifdef CONFIG_GET_CLK_FROM_ICS307
 427 /* decode S[0-2] to Output Divider (OD) */
 428 static unsigned char ics307_S_to_OD[] = {
 429         10, 2, 8, 4, 5, 7, 3, 6
 430 };
 431
 432 /* Calculate frequency being generated by ICS307-02 clock chip based upon
 433  * the control bytes being programmed into it. */
 434 /* XXX: This function should probably go into a common library */
 435 static unsigned long
 436 ics307_clk_freq(unsigned char cw0, unsigned char cw1, unsigned char cw2)
 437 {
 438         const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
 439         unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
 440         unsigned long RDW = cw2 & 0x7F;
 441         unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
 442         unsigned long freq;
 443
 444         /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
 445
 446         /* cw0:  C1 C0 TTL F1 F0 S2 S1 S0
 447          * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
 448          * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
 449          *
 450          * R6:R0 = Reference Divider Word (RDW)
 451          * V8:V0 = VCO Divider Word (VDW)
 452          * S2:S0 = Output Divider Select (OD)
 453          * F1:F0 = Function of CLK2 Output
 454          * TTL = duty cycle
 455          * C1:C0 = internal load capacitance for cyrstal
 456          */
 457
 458         /* Adding 1 to get a "nicely" rounded number, but this needs
 459          * more tweaking to get a "properly" rounded number. */
 460
 461         freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
 462
 463         debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
 464                         freq);
 465         return freq;
 466 }
 467
 468 unsigned long get_board_sys_clk(ulong dummy)
 469 {
 470         return gd->bus_clk;
 471 }
 472
 473 unsigned long get_board_ddr_clk(ulong dummy)
 474 {
 475         return gd->mem_clk;
 476 }
 477
 478 unsigned long
 479 calculate_board_sys_clk(ulong dummy)
 480 {
 481         ulong val;
 482         val = ics307_clk_freq(
 483             in8(PIXIS_BASE + PIXIS_VSYSCLK0),
 484             in8(PIXIS_BASE + PIXIS_VSYSCLK1),
 485             in8(PIXIS_BASE + PIXIS_VSYSCLK2));
 486         debug("sysclk val = %lu\n", val);
 487         return val;
 488 }
 489
 490 unsigned long
 491 calculate_board_ddr_clk(ulong dummy)
 492 {
 493         ulong val;
 494         val = ics307_clk_freq(
 495             in8(PIXIS_BASE + PIXIS_VDDRCLK0),
 496             in8(PIXIS_BASE + PIXIS_VDDRCLK1),
 497             in8(PIXIS_BASE + PIXIS_VDDRCLK2));
 498         debug("ddrclk val = %lu\n", val);
 499         return val;
 500 }
 501 #else
 502 unsigned long get_board_sys_clk(ulong dummy)
 503 {
 504         u8 i;
 505         ulong val = 0;
 506
 507         i = in8(PIXIS_BASE + PIXIS_SPD);
 508         i &= 0x07;
 509
 510         switch (i) {
 511                 case 0:
 512                         val = 33333333;
 513                         break;
 514                 case 1:
 515                         val = 40000000;
 516                         break;
 517                 case 2:
 518                         val = 50000000;
 519                         break;
 520                 case 3:
 521                         val = 66666666;
 522                         break;
 523                 case 4:
 524                         val = 83333333;
 525                         break;
 526                 case 5:
 527                         val = 100000000;
 528                         break;
 529                 case 6:
 530                         val = 133333333;
 531                         break;
 532                 case 7:
 533                         val = 166666666;
 534                         break;
 535         }
 536
 537         return val;
 538 }
 539
 540 unsigned long get_board_ddr_clk(ulong dummy)
 541 {
 542         u8 i;
 543         ulong val = 0;
 544
 545         i = in8(PIXIS_BASE + PIXIS_SPD);
 546         i &= 0x38;
 547         i >>= 3;
 548
 549         switch (i) {
 550                 case 0:
 551                         val = 33333333;
 552                         break;
 553                 case 1:
 554                         val = 40000000;
 555                         break;
 556                 case 2:
 557                         val = 50000000;
 558                         break;
 559                 case 3:
 560                         val = 66666666;
 561                         break;
 562                 case 4:
 563                         val = 83333333;
 564                         break;
 565                 case 5:
 566                         val = 100000000;
 567                         break;
 568                 case 6:
 569                         val = 133333333;
 570                         break;
 571                 case 7:
 572                         val = 166666666;
 573                         break;
 574         }
 575         return val;
 576 }
 577 #endif
 578
 579 #ifdef CONFIG_TSEC_ENET
 580 int board_eth_init(bd_t *bis)
 581 {
 582         struct tsec_info_struct tsec_info[4];
 583         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 584         int num = 0;
 585
 586 #ifdef CONFIG_TSEC1
 587         SET_STD_TSEC_INFO(tsec_info[num], 1);
 588         num++;
 589 #endif
 590 #ifdef CONFIG_TSEC2
 591         SET_STD_TSEC_INFO(tsec_info[num], 2);
 592         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 593                 tsec_info[num].flags |= TSEC_SGMII;
 594         num++;
 595 #endif
 596 #ifdef CONFIG_TSEC3
 597         SET_STD_TSEC_INFO(tsec_info[num], 3);
 598         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 599                 tsec_info[num].flags |= TSEC_SGMII;
 600         num++;
 601 #endif
 602
 603         if (!num) {
 604                 printf("No TSECs initialized\n");
 605
 606                 return 0;
 607         }
 608
 609 #ifdef CONFIG_FSL_SGMII_RISER
 610         fsl_sgmii_riser_init(tsec_info, num);
 611 #endif
 612
 613         tsec_eth_init(bis, tsec_info, num);
 614
 615         return pci_eth_init(bis);
 616 }
 617 #endif
 618
 619 #if defined(CONFIG_OF_BOARD_SETUP)
 620 void ft_board_setup(void *blob, bd_t *bd)
 621 {
 622         phys_addr_t base;
 623         phys_size_t size;
 624
 625         ft_cpu_setup(blob, bd);
 626
 627         base = getenv_bootm_low();
 628         size = getenv_bootm_size();
 629
 630         fdt_fixup_memory(blob, (u64)base, (u64)size);
 631
 632 #ifdef CONFIG_PCIE3
 633         ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
 634 #endif
 635 #ifdef CONFIG_PCIE2
 636         ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
 637 #endif
 638 #ifdef CONFIG_PCIE1
 639         ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
 640 #endif
 641 #ifdef CONFIG_FSL_SGMII_RISER
 642         fsl_sgmii_riser_fdt_fixup(blob);
 643 #endif
 644 }
 645 #endif
 646
 647 #ifdef CONFIG_MP
 648 void board_lmb_reserve(struct lmb *lmb)
 649 {
 650         cpu_mp_lmb_reserve(lmb);
 651 }
 652 #endif