2 * Copyright 2011 Freescale Semiconductor
3 * Author: Mingkai Hu <Mingkai.hu@freescale.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the Free
7 * Software Foundation; either version 2 of the License, or (at your option)
10 * This file provides support for the board-specific CPLD used on some Freescale
13 * The following macros need to be defined:
15 * CPLD_BASE - The virtual address of the base of the CPLD register map
25 static u8 __cpld_read(unsigned int reg)
27 void *p = (void *)CPLD_BASE;
31 u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read")));
33 static void __cpld_write(unsigned int reg, u8 value)
35 void *p = (void *)CPLD_BASE;
37 out_8(p + reg, value);
39 void cpld_write(unsigned int reg, u8 value)
40 __attribute__((weak, alias("__cpld_write")));
43 * Reset the board. This honors the por_cfg registers.
45 void __cpld_reset(void)
47 CPLD_WRITE(system_rst, 1);
49 void cpld_reset(void) __attribute__((weak, alias("__cpld_reset")));
52 * Set the boot bank to the alternate bank
54 void __cpld_set_altbank(void)
56 CPLD_WRITE(fbank_sel, 1);
58 void cpld_set_altbank(void)
59 __attribute__((weak, alias("__cpld_set_altbank")));
62 * Set the boot bank to the default bank
64 void __cpld_clear_altbank(void)
66 CPLD_WRITE(fbank_sel, 0);
68 void cpld_clear_altbank(void)
69 __attribute__((weak, alias("__cpld_clear_altbank")));
72 static void cpld_dump_regs(void)
74 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
75 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
76 printf("pcba_ver = 0x%02x\n", CPLD_READ(pcba_ver));
77 printf("system_rst = 0x%02x\n", CPLD_READ(system_rst));
78 printf("wd_cfg = 0x%02x\n", CPLD_READ(wd_cfg));
79 printf("sw_ctl_on = 0x%02x\n", CPLD_READ(sw_ctl_on));
80 printf("por_cfg = 0x%02x\n", CPLD_READ(por_cfg));
81 printf("switch_strobe = 0x%02x\n", CPLD_READ(switch_strobe));
82 printf("jtag_sel = 0x%02x\n", CPLD_READ(jtag_sel));
83 printf("sdbank1_clk = 0x%02x\n", CPLD_READ(sdbank1_clk));
84 printf("sdbank2_clk = 0x%02x\n", CPLD_READ(sdbank2_clk));
85 printf("fbank_sel = 0x%02x\n", CPLD_READ(fbank_sel));
86 printf("serdes_mux = 0x%02x\n", CPLD_READ(serdes_mux));
87 printf("SW[2] = 0x%02x\n", in_8(&CPLD_SW(2)));
92 int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
98 return cmd_usage(cmdtp);
100 if (strcmp(argv[1], "reset") == 0) {
101 if (strcmp(argv[2], "altbank") == 0)
104 cpld_clear_altbank();
107 } else if (strcmp(argv[1], "watchdog") == 0) {
108 static char *period[8] = {"1ms", "10ms", "30ms", "disable",
109 "100ms", "1s", "10s", "60s"};
110 for (i = 0; i < ARRAY_SIZE(period); i++) {
111 if (strcmp(argv[2], period[i]) == 0)
112 CPLD_WRITE(wd_cfg, i);
114 } else if (strcmp(argv[1], "lane_mux") == 0) {
115 u32 lane = simple_strtoul(argv[2], NULL, 16);
116 u8 val = (u8)simple_strtoul(argv[3], NULL, 16);
117 u8 reg = CPLD_READ(serdes_mux);
121 reg &= ~SERDES_MUX_LANE_6_MASK;
122 reg |= val << SERDES_MUX_LANE_6_SHIFT;
125 reg &= ~SERDES_MUX_LANE_A_MASK;
126 reg |= val << SERDES_MUX_LANE_A_SHIFT;
129 reg &= ~SERDES_MUX_LANE_C_MASK;
130 reg |= val << SERDES_MUX_LANE_C_SHIFT;
133 reg &= ~SERDES_MUX_LANE_D_MASK;
134 reg |= val << SERDES_MUX_LANE_D_SHIFT;
137 printf("Invalid value\n");
141 CPLD_WRITE(serdes_mux, reg);
143 } else if (strcmp(argv[1], "dump") == 0) {
147 rc = cmd_usage(cmdtp);
153 cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd,
154 "Reset the board or pin mulexing selection using the CPLD sequencer",
155 "reset - hard reset to default bank\n"
156 "cpld_cmd reset altbank - reset to alternate bank\n"
157 "cpld_cmd watchdog <watchdog_period> - set the watchdog period\n"
158 " period: 1ms 10ms 30ms 100ms 1s 10s 60s disable\n"
159 "cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n"
160 " lane 6: 0 -> slot1 (Default)\n"
162 " lane a: 0 -> slot2 (Default)\n"
164 " lane c: 0 -> slot2 (Default)\n"
166 " lane d: 0 -> slot2 (Default)\n"
169 "cpld_cmd dump - display the CPLD registers\n"