2 * Copyright 2011 Freescale Semiconductor
3 * Author: Mingkai Hu <Mingkai.hu@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
7 * This file provides support for the ngPIXIS, a board-specific FPGA used on
8 * some Freescale reference boards.
12 * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
14 typedef struct cpld_data {
15 u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */
16 u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */
17 u8 pcba_ver; /* 0x2 - PCBA Revision Register */
18 u8 system_rst; /* 0x3 - system reset register */
19 u8 res0; /* 0x4 - not used */
20 u8 sw_ctl_on; /* 0x5 - Switch Control Enable Register */
21 u8 por_cfg; /* 0x6 - POR Control Register */
22 u8 switch_strobe; /* 0x7 - Multiplexed pin Select Register */
23 u8 jtag_sel; /* 0x8 - JTAG or AURORA Selection */
24 u8 sdbank1_clk; /* 0x9 - SerDes Bank1 Reference clock */
25 u8 sdbank2_clk; /* 0xa - SerDes Bank2 Reference clock */
26 u8 fbank_sel; /* 0xb - Flash bank selection */
27 u8 serdes_mux; /* 0xc - Multiplexed pin Select Register */
28 u8 sw[1]; /* 0xd - SW2 Status */
29 u8 system_rst_default; /* 0xe - system reset to default register */
30 u8 sysclk_sw1; /* 0xf - sysclk configuration register */
31 } __attribute__ ((packed)) cpld_data_t;
33 #define SERDES_MUX_LANE_6_MASK 0x2
34 #define SERDES_MUX_LANE_6_SHIFT 1
35 #define SERDES_MUX_LANE_A_MASK 0x1
36 #define SERDES_MUX_LANE_A_SHIFT 0
37 #define SERDES_MUX_LANE_C_MASK 0x4
38 #define SERDES_MUX_LANE_C_SHIFT 2
39 #define SERDES_MUX_LANE_D_MASK 0x8
40 #define SERDES_MUX_LANE_D_SHIFT 3
41 #define CPLD_SWITCH_BANK_ENABLE 0x40
42 #define CPLD_SYSCLK_83 0x1 /* system clock 83.3MHz */
43 #define CPLD_SYSCLK_100 0x2 /* system clock 100MHz */
45 /* Pointer to the CPLD register set */
46 #define cpld ((cpld_data_t *)CPLD_BASE)
48 /* The CPLD SW register that corresponds to board switch X, where x >= 1 */
49 #define CPLD_SW(x) (cpld->sw[(x) - 2])
51 u8 cpld_read(unsigned int reg);
52 void cpld_write(unsigned int reg, u8 value);
54 #define CPLD_READ(reg) cpld_read(offsetof(cpld_data_t, reg))
55 #define CPLD_WRITE(reg, value) cpld_write(offsetof(cpld_data_t, reg), value)