2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <linux/compiler.h>
28 #include <asm/processor.h>
29 #include <asm/cache.h>
30 #include <asm/immap_85xx.h>
31 #include <asm/fsl_law.h>
32 #include <asm/fsl_serdes.h>
33 #include <asm/fsl_portals.h>
34 #include <asm/fsl_liodn.h>
36 #include <configs/P3060QDS.h>
38 #include <fdt_support.h>
40 #include "../common/qixis.h"
42 #include "p3060qds_qixis.h"
44 DECLARE_GLOBAL_DATA_PTR;
49 struct cpu_type *cpu = gd->cpu;
50 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
53 printf("Board: %s", cpu->name);
56 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
57 QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
59 sw = QIXIS_READ(brdcfg[0]);
60 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
63 printf("vBank: %d\n", sw);
69 printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
71 #ifdef CONFIG_PHYS_64BIT
72 puts("36-bit Addressing\n");
74 puts("Reset Configuration Word (RCW):");
75 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
76 u32 rcw = in_be32(&gur->rcwsr[i]);
79 printf("\n %08x:", i * 4);
84 puts("SERDES Reference Clocks: ");
85 sw = QIXIS_READ(brdcfg[2]);
86 for (i = 0; i < 3; i++) {
87 static const char * const freq[] = {"100", "125", "Reserved",
89 unsigned int clock = (sw >> (2 * i)) & 3;
91 printf("Bank%u=%sMhz ", i+1, freq[clock]);
98 int board_early_init_f(void)
100 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
102 /* only single DDR controller on QDS board, disable DDR1_MCK4/5 */
103 setbits_be32(&gur->ddrclkdr, 0x00030000);
108 void board_config_serdes_mux(void)
110 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
111 int cfg = (in_be32(&gur->rcwsr[4]) &
112 FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
117 /* set Lane I,J as SGMII */
118 QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_B | BRDCFG6_SD3MX_A |
119 BRDCFG6_SD2MX_B | BRDCFG6_SD1MX_A);
124 /* set Lane I,J as Aurora Debug */
125 QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_A | BRDCFG6_SD3MX_B |
126 BRDCFG6_SD2MX_A | BRDCFG6_SD1MX_B);
129 puts("Invalid SerDes protocol for P3060QDS\n");
134 void board_config_usb_mux(void)
136 u8 brdcfg4, brdcfg5, brdcfg7;
137 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
138 u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
139 u32 ec1 = rcwsr11 & FSL_CORENET_RCWSR11_EC1;
140 u32 ec2 = rcwsr11 & FSL_CORENET_RCWSR11_EC2;
142 brdcfg4 = QIXIS_READ(brdcfg[4]);
143 brdcfg4 &= ~BRDCFG4_EC_MODE_MASK;
144 if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) &&
145 (ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) {
146 brdcfg4 |= BRDCFG4_EC2_USB_EC1_USB;
148 } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) &&
149 ((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) ||
150 (ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) {
151 brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_USB;
153 } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) &&
154 (ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) {
155 brdcfg4 |= BRDCFG4_EC2_USB_EC1_RGMII;
157 } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) &&
158 ((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) ||
159 (ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) {
160 brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_RGMII;
162 brdcfg4 |= BRDCFG4_EC2_MII_EC1_MII;
164 QIXIS_WRITE(brdcfg[4], brdcfg4);
166 brdcfg5 = QIXIS_READ(brdcfg[5]);
167 brdcfg5 &= ~(BRDCFG5_USB1ID_MASK | BRDCFG5_USB2ID_MASK);
168 brdcfg5 |= (BRDCFG5_USB1ID_CTRL | BRDCFG5_USB2ID_CTRL);
169 QIXIS_WRITE(brdcfg[5], brdcfg5);
171 brdcfg7 = BRDCFG7_JTAGMX_COP_JTAG | BRDCFG7_IQ1MX_IRQ_EVT |
172 BRDCFG7_G1MX_USB1 | BRDCFG7_D1MX_TSEC3USB | BRDCFG7_I3MX_USB1;
173 QIXIS_WRITE(brdcfg[7], brdcfg7);
176 int board_early_init_r(void)
178 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
179 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
182 * Remap Boot flash + PROMJET region to caching-inhibited
183 * so that flash can be erased properly.
186 /* Flush d-cache and invalidate i-cache of any FLASH data */
190 /* invalidate existing TLB entry for flash + promjet */
191 disable_tlb(flash_esel);
193 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
194 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
195 0, flash_esel, BOOKE_PAGESZ_256M, 1);
198 #ifdef CONFIG_SYS_DPAA_QBMAN
201 board_config_serdes_mux();
202 board_config_usb_mux();
207 static const char *serdes_clock_to_string(u32 clock)
210 case SRDS_PLLCR0_RFCK_SEL_100:
212 case SRDS_PLLCR0_RFCK_SEL_125:
214 case SRDS_PLLCR0_RFCK_SEL_156_25:
221 #define NUM_SRDS_BANKS 3
223 int misc_init_r(void)
225 serdes_corenet_t *srds_regs;
226 u32 actual[NUM_SRDS_BANKS];
230 sw = QIXIS_READ(brdcfg[2]);
231 for (i = 0; i < 3; i++) {
232 unsigned int clock = (sw >> (2 * i)) & 3;
235 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
238 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
241 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
244 printf("Warning: SDREFCLK%u switch setting of '10' is "
245 "unsupported\n", i + 1);
250 srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
251 for (i = 0; i < NUM_SRDS_BANKS; i++) {
252 u32 pllcr0 = in_be32(&srds_regs->bank[i].pllcr0);
253 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
254 if (expected != actual[i]) {
255 printf("Warning: SERDES bank %u expects reference clock"
256 " %sMHz, but actual is %sMHz\n", i + 1,
257 serdes_clock_to_string(expected),
258 serdes_clock_to_string(actual[i]));
266 * This is map of CVDD values. 33 means CVDD is 3.3v, 25 means CVDD is 2.5v,
267 * 18 means CVDD is 1.8v.
269 static u8 IO_VSEL[] = {
270 33, 33, 33, 25, 25, 25, 18, 18, 18,
271 33, 33, 33, 25, 25, 25, 18, 18, 18,
272 33, 33, 33, 25, 25, 25, 18, 18, 18,
276 #define IO_VSEL_MASK 0x1f
279 * different CVDD selects diffenert spi flashs, read dutcfg[3] to get CVDD,
280 * then set status of spi flash nodes to 'disabled' according to CVDD.
281 * CVDD '33' will select spi flash0 and flash1, CVDD '25' will select spi
282 * flash2, CVDD '18' will select spi flash3.
284 void fdt_fixup_board_spi(void *blob)
286 u8 sw5 = QIXIS_READ(dutcfg[3]);
288 switch (IO_VSEL[sw5 & IO_VSEL_MASK]) {
291 do_fixup_by_compat(blob, "atmel,at45db081d", "status",
292 "disabled", strlen("disabled") + 1, 1);
293 do_fixup_by_compat(blob, "spansion,sst25wf040", "status",
294 "disabled", strlen("disabled") + 1, 1);
298 do_fixup_by_compat(blob, "spansion,s25sl12801", "status",
299 "disabled", strlen("disabled") + 1, 1);
300 do_fixup_by_compat(blob, "spansion,en25q32", "status",
301 "disabled", strlen("disabled") + 1, 1);
302 do_fixup_by_compat(blob, "spansion,sst25wf040", "status",
303 "disabled", strlen("disabled") + 1, 1);
307 do_fixup_by_compat(blob, "spansion,s25sl12801", "status",
308 "disabled", strlen("disabled") + 1, 1);
309 do_fixup_by_compat(blob, "spansion,en25q32", "status",
310 "disabled", strlen("disabled") + 1, 1);
311 do_fixup_by_compat(blob, "atmel,at45db081d", "status",
312 "disabled", strlen("disabled") + 1, 1);
317 void ft_board_setup(void *blob, bd_t *bd)
322 ft_cpu_setup(blob, bd);
324 base = getenv_bootm_low();
325 size = getenv_bootm_size();
327 fdt_fixup_memory(blob, (u64)base, (u64)size);
330 pci_of_setup(blob, bd);
333 fdt_fixup_liodn(blob);
334 fdt_fixup_dr_usb(blob, bd);
335 fdt_fixup_board_spi(blob);
337 #ifdef CONFIG_SYS_DPAA_FMAN
338 fdt_fixup_fman_ethernet(blob);
339 fdt_fixup_board_enet(blob);