1 /* Copyright 2014 Freescale Semiconductor, Inc.
3 * SPDX-License-Identifier: GPL-2.0+
13 #include <fsl_esdhc.h>
14 #include <spi_flash.h>
15 #include "../common/qixis.h"
16 #include "t102xqds_qixis.h"
18 DECLARE_GLOBAL_DATA_PTR;
20 phys_size_t get_effective_memsize(void)
22 return CONFIG_SYS_L3_SIZE;
25 unsigned long get_board_sys_clk(void)
27 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
29 switch (sysclk_conf & 0x0F) {
32 case QIXIS_SYSCLK_100:
34 case QIXIS_SYSCLK_125:
36 case QIXIS_SYSCLK_133:
38 case QIXIS_SYSCLK_150:
40 case QIXIS_SYSCLK_160:
42 case QIXIS_SYSCLK_166:
48 unsigned long get_board_ddr_clk(void)
50 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
52 switch ((ddrclk_conf & 0x30) >> 4) {
53 case QIXIS_DDRCLK_100:
55 case QIXIS_DDRCLK_125:
57 case QIXIS_DDRCLK_133:
63 void board_init_f(ulong bootflag)
65 u32 plat_ratio, sys_clk, ccb_clk;
66 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
68 #if defined(CONFIG_PPC_T1040) && defined(CONFIG_SPL_NAND_BOOT)
70 * There is T1040 SoC issue where NOR, FPGA are inaccessible during
71 * NAND boot because IFC signals > IFC_AD7 are not enabled.
72 * This workaround changes RCW source to make all signals enabled.
75 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
77 porsr1 = in_be32(&gur->porsr1);
78 pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
79 out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
82 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
83 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
85 /* Update GD pointer */
86 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
90 /* initialize selected port with appropriate baud rate */
91 sys_clk = get_board_sys_clk();
92 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
93 ccb_clk = sys_clk * plat_ratio / 2;
95 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
96 ccb_clk / 16 / CONFIG_BAUDRATE);
98 #if defined(CONFIG_SPL_MMC_BOOT)
99 puts("\nSD boot...\n");
100 #elif defined(CONFIG_SPL_SPI_BOOT)
101 puts("\nSPI boot...\n");
102 #elif defined(CONFIG_SPL_NAND_BOOT)
103 puts("\nNAND boot...\n");
106 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
109 void board_init_r(gd_t *gd, ulong dest_addr)
113 bd = (bd_t *)(gd + sizeof(gd_t));
114 memset(bd, 0, sizeof(bd_t));
116 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
117 bd->bi_memsize = CONFIG_SYS_L3_SIZE;
121 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
122 CONFIG_SPL_RELOC_MALLOC_SIZE);
124 #ifdef CONFIG_SPL_NAND_BOOT
125 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
126 (uchar *)CONFIG_ENV_ADDR);
128 #ifdef CONFIG_SPL_MMC_BOOT
130 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
131 (uchar *)CONFIG_ENV_ADDR);
133 #ifdef CONFIG_SPL_SPI_BOOT
134 spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
135 (uchar *)CONFIG_ENV_ADDR);
138 gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
143 gd->ram_size = initdram(0);
145 #ifdef CONFIG_SPL_MMC_BOOT
147 #elif defined(CONFIG_SPL_SPI_BOOT)
149 #elif defined(CONFIG_SPL_NAND_BOOT)