1 /* Copyright 2014 Freescale Semiconductor, Inc.
3 * SPDX-License-Identifier: GPL-2.0+
12 #include <fsl_esdhc.h>
13 #include <spi_flash.h>
14 #include "../common/qixis.h"
15 #include "t102xqds_qixis.h"
17 DECLARE_GLOBAL_DATA_PTR;
19 phys_size_t get_effective_memsize(void)
21 return CONFIG_SYS_L3_SIZE;
24 unsigned long get_board_sys_clk(void)
26 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
28 switch (sysclk_conf & 0x0F) {
31 case QIXIS_SYSCLK_100:
33 case QIXIS_SYSCLK_125:
35 case QIXIS_SYSCLK_133:
37 case QIXIS_SYSCLK_150:
39 case QIXIS_SYSCLK_160:
41 case QIXIS_SYSCLK_166:
47 unsigned long get_board_ddr_clk(void)
49 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
51 switch ((ddrclk_conf & 0x30) >> 4) {
52 case QIXIS_DDRCLK_100:
54 case QIXIS_DDRCLK_125:
56 case QIXIS_DDRCLK_133:
62 void board_init_f(ulong bootflag)
64 u32 plat_ratio, sys_clk, ccb_clk;
65 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
67 #if defined(CONFIG_PPC_T1040) && defined(CONFIG_SPL_NAND_BOOT)
69 * There is T1040 SoC issue where NOR, FPGA are inaccessible during
70 * NAND boot because IFC signals > IFC_AD7 are not enabled.
71 * This workaround changes RCW source to make all signals enabled.
74 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
76 porsr1 = in_be32(&gur->porsr1);
77 pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
78 out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
81 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
82 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
84 /* Update GD pointer */
85 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
89 /* initialize selected port with appropriate baud rate */
90 sys_clk = get_board_sys_clk();
91 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
92 ccb_clk = sys_clk * plat_ratio / 2;
94 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
95 ccb_clk / 16 / CONFIG_BAUDRATE);
97 #if defined(CONFIG_SPL_MMC_BOOT)
98 puts("\nSD boot...\n");
99 #elif defined(CONFIG_SPL_SPI_BOOT)
100 puts("\nSPI boot...\n");
101 #elif defined(CONFIG_SPL_NAND_BOOT)
102 puts("\nNAND boot...\n");
105 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
108 void board_init_r(gd_t *gd, ulong dest_addr)
112 bd = (bd_t *)(gd + sizeof(gd_t));
113 memset(bd, 0, sizeof(bd_t));
115 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
116 bd->bi_memsize = CONFIG_SYS_L3_SIZE;
120 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
121 CONFIG_SPL_RELOC_MALLOC_SIZE);
123 #ifdef CONFIG_SPL_NAND_BOOT
124 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
125 (uchar *)CONFIG_ENV_ADDR);
127 #ifdef CONFIG_SPL_MMC_BOOT
129 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
130 (uchar *)CONFIG_ENV_ADDR);
132 #ifdef CONFIG_SPL_SPI_BOOT
133 spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
134 (uchar *)CONFIG_ENV_ADDR);
137 gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
142 gd->ram_size = initdram(0);
144 #ifdef CONFIG_SPL_MMC_BOOT
146 #elif defined(CONFIG_SPL_SPI_BOOT)
148 #elif defined(CONFIG_SPL_NAND_BOOT)