2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
13 #include <asm/processor.h>
14 #include <asm/cache.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_law.h>
17 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_portals.h>
19 #include <asm/fsl_liodn.h>
22 #include <asm/mpc85xx_gpio.h>
23 #include "../common/qixis.h"
25 #include "t102xqds_qixis.h"
27 DECLARE_GLOBAL_DATA_PTR;
32 struct cpu_type *cpu = gd->arch.cpu;
33 static const char *const freq[] = {"100", "125", "156.25", "100.0"};
35 u8 sw = QIXIS_READ(arch);
37 printf("Board: %sQDS, ", cpu->name);
38 printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
39 printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
46 sw = QIXIS_READ(brdcfg[0]);
47 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
50 printf("vBank: %d\n", sw);
58 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
61 printf("FPGA: v%d (%s), build %d",
62 (int)QIXIS_READ(scver), qixis_read_tag(buf),
63 (int)qixis_read_minor());
64 /* the timestamp string contains "\n" at the end */
65 printf(" on %s", qixis_read_time(buf));
67 puts("SERDES Reference: ");
68 sw = QIXIS_READ(brdcfg[2]);
69 clock = (sw >> 6) & 3;
70 printf("Clock1=%sMHz ", freq[clock]);
71 clock = (sw >> 4) & 3;
72 printf("Clock2=%sMHz\n", freq[clock]);
77 int select_i2c_ch_pca9547(u8 ch)
81 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
83 puts("PCA: failed to select proper channel\n");
90 static int board_mux_lane_to_slot(void)
92 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
96 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
97 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
98 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
101 brdcfg9 = QIXIS_READ(brdcfg[9]);
102 QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE);
104 switch (srds_prtcl_s1) {
106 /* SerDes1 is not enabled */
114 QIXIS_WRITE(brdcfg[12], 0x8c);
117 QIXIS_WRITE(brdcfg[12], 0xfc);
123 QIXIS_WRITE(brdcfg[12], 0x88);
126 QIXIS_WRITE(brdcfg[12], 0xcc);
129 QIXIS_WRITE(brdcfg[12], 0xc8);
133 brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
134 QIXIS_WRITE(brdcfg[9], brdcfg9);
135 QIXIS_WRITE(brdcfg[12], 0x8c);
138 QIXIS_WRITE(brdcfg[12], 0x00);
144 /* Aurora, PCIe, SGMII, SATA */
145 QIXIS_WRITE(brdcfg[12], 0x04);
148 printf("WARNING: unsupported for SerDes Protocol %d\n",
156 #ifdef CONFIG_PPC_T1024
157 static void board_mux_setup(void)
161 brdcfg15 = QIXIS_READ(brdcfg[15]);
162 brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;
164 if (hwconfig_arg_cmp("pin_mux", "tdm")) {
165 /* Route QE_TDM multiplexed signals to TDM Riser slot */
166 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM);
167 QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
168 } else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
169 /* to UCC (ProfiBus) interface */
170 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC);
171 } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
172 /* to DVI (HDMI) encoder */
173 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI);
174 } else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
175 /* to DFP (LCD) encoder */
176 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM |
177 BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD);
182 int board_early_init_r(void)
184 #ifdef CONFIG_SYS_FLASH_BASE
185 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
186 int flash_esel = find_tlb_idx((void *)flashbase, 1);
189 * Remap Boot flash + PROMJET region to caching-inhibited
190 * so that flash can be erased properly.
193 /* Flush d-cache and invalidate i-cache of any FLASH data */
197 if (flash_esel == -1) {
198 /* very unlikely unless something is messed up */
199 puts("Error: Could not find TLB for FLASH BASE\n");
200 flash_esel = 2; /* give our best effort to continue */
202 /* invalidate existing TLB entry for flash + promjet */
203 disable_tlb(flash_esel);
206 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
207 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
208 0, flash_esel, BOOKE_PAGESZ_256M, 1);
211 #ifdef CONFIG_SYS_DPAA_QBMAN
214 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
215 board_mux_lane_to_slot();
219 unsigned long get_board_sys_clk(void)
221 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
223 switch (sysclk_conf & 0x0F) {
224 case QIXIS_SYSCLK_64:
226 case QIXIS_SYSCLK_83:
228 case QIXIS_SYSCLK_100:
230 case QIXIS_SYSCLK_125:
232 case QIXIS_SYSCLK_133:
234 case QIXIS_SYSCLK_150:
236 case QIXIS_SYSCLK_160:
238 case QIXIS_SYSCLK_166:
244 unsigned long get_board_ddr_clk(void)
246 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
248 switch ((ddrclk_conf & 0x30) >> 4) {
249 case QIXIS_DDRCLK_100:
251 case QIXIS_DDRCLK_125:
253 case QIXIS_DDRCLK_133:
259 #define NUM_SRDS_PLL 2
260 int misc_init_r(void)
262 #ifdef CONFIG_PPC_T1024
268 int ft_board_setup(void *blob, bd_t *bd)
273 ft_cpu_setup(blob, bd);
275 base = getenv_bootm_low();
276 size = getenv_bootm_size();
278 fdt_fixup_memory(blob, (u64)base, (u64)size);
281 pci_of_setup(blob, bd);
284 fdt_fixup_liodn(blob);
286 #ifdef CONFIG_HAS_FSL_DR_USB
287 fdt_fixup_dr_usb(blob, bd);
290 #ifdef CONFIG_SYS_DPAA_FMAN
291 fdt_fixup_fman_ethernet(blob);
292 fdt_fixup_board_enet(blob);
298 void qixis_dump_switch(void)
302 QIXIS_WRITE(cms[0], 0x00);
303 nr_of_cfgsw = QIXIS_READ(cms[1]);
305 puts("DIP switch settings dump:\n");
306 for (i = 1; i <= nr_of_cfgsw; i++) {
307 QIXIS_WRITE(cms[0], i);
308 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
312 #ifdef CONFIG_DEEP_SLEEP
313 void board_mem_sleep_setup(void)
315 /* does not provide HW signals for power management */
316 QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
317 /* Disable MCKE isolation */
318 gpio_set_value(2, 0);