2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
13 #include <asm/processor.h>
14 #include <asm/cache.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_law.h>
17 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_portals.h>
19 #include <asm/fsl_liodn.h>
22 #include <asm/mpc85xx_gpio.h>
23 #include "../common/qixis.h"
25 #include "t102xqds_qixis.h"
27 DECLARE_GLOBAL_DATA_PTR;
32 struct cpu_type *cpu = gd->arch.cpu;
33 static const char *const freq[] = {"100", "125", "156.25", "100.0"};
35 u8 sw = QIXIS_READ(arch);
37 printf("Board: %sQDS, ", cpu->name);
38 printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
39 printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
46 sw = QIXIS_READ(brdcfg[0]);
47 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
50 printf("vBank: %d\n", sw);
58 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
61 printf("FPGA: v%d (%s), build %d",
62 (int)QIXIS_READ(scver), qixis_read_tag(buf),
63 (int)qixis_read_minor());
64 /* the timestamp string contains "\n" at the end */
65 printf(" on %s", qixis_read_time(buf));
67 puts("SERDES Reference: ");
68 sw = QIXIS_READ(brdcfg[2]);
69 clock = (sw >> 6) & 3;
70 printf("Clock1=%sMHz ", freq[clock]);
71 clock = (sw >> 4) & 3;
72 printf("Clock2=%sMHz\n", freq[clock]);
77 int select_i2c_ch_pca9547(u8 ch)
81 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
83 puts("PCA: failed to select proper channel\n");
90 static int board_mux_lane_to_slot(void)
92 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
96 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
97 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
98 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
101 brdcfg9 = QIXIS_READ(brdcfg[9]);
102 QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE);
104 switch (srds_prtcl_s1) {
106 /* SerDes1 is not enabled */
114 QIXIS_WRITE(brdcfg[12], 0x8c);
117 QIXIS_WRITE(brdcfg[12], 0xfc);
123 QIXIS_WRITE(brdcfg[12], 0x88);
126 QIXIS_WRITE(brdcfg[12], 0xcc);
129 QIXIS_WRITE(brdcfg[12], 0xc8);
133 brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
134 QIXIS_WRITE(brdcfg[9], brdcfg9);
135 QIXIS_WRITE(brdcfg[12], 0x8c);
138 QIXIS_WRITE(brdcfg[12], 0x00);
144 /* Aurora, PCIe, SGMII, SATA */
145 QIXIS_WRITE(brdcfg[12], 0x04);
148 printf("WARNING: unsupported for SerDes Protocol %d\n",
156 #ifdef CONFIG_PPC_T1024
157 static void board_mux_setup(void)
161 brdcfg15 = QIXIS_READ(brdcfg[15]);
162 brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;
164 if (hwconfig_arg_cmp("pin_mux", "tdm")) {
165 /* Route QE_TDM multiplexed signals to TDM Riser slot */
166 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM);
167 QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
168 QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
169 ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM);
170 } else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
171 /* to UCC (ProfiBus) interface */
172 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC);
173 } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
174 /* to DVI (HDMI) encoder */
175 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI);
176 } else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
177 /* to DFP (LCD) encoder */
178 QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM |
179 BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD);
182 if (hwconfig_arg_cmp("adaptor", "sdxc"))
183 /* Route SPI_CS multiplexed signals to SD slot */
184 QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
185 ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC);
189 void board_retimer_ds125df111_init(void)
193 /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
195 i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1);
197 i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1);
199 /* Access to Control/Shared register */
201 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
203 /* Read device revision and ID */
204 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
205 debug("Retimer version id = 0x%x\n", reg);
207 /* Enable Broadcast */
209 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
211 /* Reset Channel Registers */
212 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
214 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
216 /* Enable override divider select and Enable Override Output Mux */
217 i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1);
219 i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1);
221 /* Select VCO Divider to full rate (000) */
222 i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
224 i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
226 /* Select active PFD MUX input as re-timed data (001) */
227 i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
230 i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
232 /* Set data rate as 10.3125 Gbps */
234 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
236 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
238 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
240 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
242 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
245 int board_early_init_r(void)
247 #ifdef CONFIG_SYS_FLASH_BASE
248 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
249 int flash_esel = find_tlb_idx((void *)flashbase, 1);
252 * Remap Boot flash + PROMJET region to caching-inhibited
253 * so that flash can be erased properly.
256 /* Flush d-cache and invalidate i-cache of any FLASH data */
260 if (flash_esel == -1) {
261 /* very unlikely unless something is messed up */
262 puts("Error: Could not find TLB for FLASH BASE\n");
263 flash_esel = 2; /* give our best effort to continue */
265 /* invalidate existing TLB entry for flash + promjet */
266 disable_tlb(flash_esel);
269 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
270 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
271 0, flash_esel, BOOKE_PAGESZ_256M, 1);
274 #ifdef CONFIG_SYS_DPAA_QBMAN
277 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
278 board_mux_lane_to_slot();
279 board_retimer_ds125df111_init();
281 /* Increase IO drive strength to address FCS error on RGMII */
282 out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800);
287 unsigned long get_board_sys_clk(void)
289 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
291 switch (sysclk_conf & 0x0F) {
292 case QIXIS_SYSCLK_64:
294 case QIXIS_SYSCLK_83:
296 case QIXIS_SYSCLK_100:
298 case QIXIS_SYSCLK_125:
300 case QIXIS_SYSCLK_133:
302 case QIXIS_SYSCLK_150:
304 case QIXIS_SYSCLK_160:
306 case QIXIS_SYSCLK_166:
312 unsigned long get_board_ddr_clk(void)
314 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
316 switch ((ddrclk_conf & 0x30) >> 4) {
317 case QIXIS_DDRCLK_100:
319 case QIXIS_DDRCLK_125:
321 case QIXIS_DDRCLK_133:
327 #define NUM_SRDS_PLL 2
328 int misc_init_r(void)
330 #ifdef CONFIG_PPC_T1024
336 void fdt_fixup_spi_mux(void *blob)
340 if (hwconfig_arg_cmp("pin_mux", "tdm")) {
341 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
342 "eon,en25s64")) >= 0) {
343 fdt_del_node(blob, nodeoff);
346 /* remove tdm node */
347 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
348 "maxim,ds26522")) >= 0) {
349 fdt_del_node(blob, nodeoff);
354 int ft_board_setup(void *blob, bd_t *bd)
359 ft_cpu_setup(blob, bd);
361 base = getenv_bootm_low();
362 size = getenv_bootm_size();
364 fdt_fixup_memory(blob, (u64)base, (u64)size);
367 pci_of_setup(blob, bd);
370 fdt_fixup_liodn(blob);
372 #ifdef CONFIG_HAS_FSL_DR_USB
373 fdt_fixup_dr_usb(blob, bd);
376 #ifdef CONFIG_SYS_DPAA_FMAN
377 fdt_fixup_fman_ethernet(blob);
378 fdt_fixup_board_enet(blob);
380 fdt_fixup_spi_mux(blob);
385 void qixis_dump_switch(void)
389 QIXIS_WRITE(cms[0], 0x00);
390 nr_of_cfgsw = QIXIS_READ(cms[1]);
392 puts("DIP switch settings dump:\n");
393 for (i = 1; i <= nr_of_cfgsw; i++) {
394 QIXIS_WRITE(cms[0], i);
395 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
399 #ifdef CONFIG_DEEP_SLEEP
400 void board_mem_sleep_setup(void)
402 /* does not provide HW signals for power management */
403 QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
404 /* Disable MCKE isolation */
405 gpio_set_value(2, 0);