2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __T1024QDS_QIXIS_H__
8 #define __T1024QDS_QIXIS_H__
10 /* Definitions of QIXIS Registers for T1024/T1023 QDS */
12 /* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
13 #define BRDCFG4_EMISEL_MASK 0xE0
14 #define BRDCFG4_EMISEL_SHIFT 5
16 /* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/
17 #define BRDCFG5_IMX_MASK 0xC0
18 #define BRDCFG5_IMX_DIU 0x80
20 #define BRDCFG5_SPIRTE_MASK 0x07
21 #define BRDCFG5_SPIRTE_TDM 0x01
22 #define BRDCFG5_SPIRTE_SDHC 0x02
23 #define BRDCFG9_XFI_TX_DISABLE 0x10
25 /* BRDCFG13[0:5] TDM configuration and setup */
26 #define BRDCFG13_TDM_MASK 0xfc
27 #define BRDCFG13_TDM_INTERFACE 0x37
28 #define BRDCFG13_HDLC_LOOPBACK 0x29
29 #define BRDCFG13_TDM_LOOPBACK 0x31
31 /* BRDCFG15[3] controls LCD Panel Powerdown */
32 #define BRDCFG15_LCDFM 0x20
33 #define BRDCFG15_LCDPD 0x10
34 #define BRDCFG15_LCDPD_MASK 0x10
35 #define BRDCFG15_LCDPD_ENABLED 0x00
37 /* BRDCFG15[6:7] controls DIU MUX selction*/
38 #define BRDCFG15_DIUSEL_MASK 0x03
39 #define BRDCFG15_DIUSEL_HDMI 0x00
40 #define BRDCFG15_DIUSEL_LCD 0x01
41 #define BRDCFG15_DIUSEL_UCC 0x02
42 #define BRDCFG15_DIUSEL_TDM 0x03
45 #define QIXIS_SYSCLK_66 0x0
46 #define QIXIS_SYSCLK_83 0x1
47 #define QIXIS_SYSCLK_100 0x2
48 #define QIXIS_SYSCLK_125 0x3
49 #define QIXIS_SYSCLK_133 0x4
50 #define QIXIS_SYSCLK_150 0x5
51 #define QIXIS_SYSCLK_160 0x6
52 #define QIXIS_SYSCLK_166 0x7
53 #define QIXIS_SYSCLK_64 0x8
56 #define QIXIS_DDRCLK_66 0x0
57 #define QIXIS_DDRCLK_100 0x1
58 #define QIXIS_DDRCLK_125 0x2
59 #define QIXIS_DDRCLK_133 0x3
62 #define QIXIS_SRDS1CLK_122 0x5a
63 #define QIXIS_SRDS1CLK_125 0x5e