1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 Freescale Semiconductor, Inc.
10 #include <fsl_ddr_sdram.h>
11 #include <fsl_ddr_dimm_params.h>
12 #include <asm/fsl_law.h>
13 #include <asm/mpc85xx_gpio.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 struct board_specific_parameters {
19 u32 datarate_mhz_high;
28 * datarate_mhz_high values need to be in ascending order
30 static const struct board_specific_parameters udimm0[] = {
33 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
34 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
36 {2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
37 {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
38 {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
39 {1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
40 {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
41 {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
45 static const struct board_specific_parameters *udimms[] = {
49 void fsl_ddr_board_options(memctl_options_t *popts,
51 unsigned int ctrl_num)
53 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
55 struct cpu_type *cpu = gd->arch.cpu;
58 printf("Not supported controller number %d\n", ctrl_num);
66 /* Get clk_adjust according to the board ddr freqency and n_banks
67 * specified in board_specific_parameters table.
69 ddr_freq = get_ddr_freq(0) / 1000000;
70 while (pbsp->datarate_mhz_high) {
71 if (pbsp->n_ranks == pdimm->n_ranks &&
72 (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
73 if (ddr_freq <= pbsp->datarate_mhz_high) {
74 popts->clk_adjust = pbsp->clk_adjust;
75 popts->wrlvl_start = pbsp->wrlvl_start;
76 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
77 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
86 printf("Error: board specific timing not found\n");
87 printf("for data rate %lu MT/s\n", ddr_freq);
88 printf("Trying to use the highest speed (%u) parameters\n",
89 pbsp_highest->datarate_mhz_high);
90 popts->clk_adjust = pbsp_highest->clk_adjust;
91 popts->wrlvl_start = pbsp_highest->wrlvl_start;
92 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
93 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
95 panic("DIMM is not supported by this board");
98 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
99 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
100 debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
101 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
102 debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
105 * Factors to consider for half-strength driver enable:
106 * - number of DIMMs installed
108 popts->half_strength_driver_enable = 0;
110 * Write leveling override
112 popts->wrlvl_override = 1;
113 popts->wrlvl_sample = 0xf;
116 * rtt and rtt_wr override
118 popts->rtt_override = 0;
120 /* Enable ZQ calibration */
123 /* DHC_EN =1, ODT = 75 Ohm */
124 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
125 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
127 /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
128 * force DDR bus width to 32bit for T1023
130 if (cpu->soc_ver == SVR_T1023)
131 popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
133 #ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
134 /* for DDR bus 32bit test on T1024 */
135 popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
138 #ifdef CONFIG_TARGET_T1023RDB
139 popts->wrlvl_ctl_2 = 0x07070606;
140 popts->half_strength_driver_enable = 1;
141 popts->cpo_sample = 0x43;
142 #elif defined(CONFIG_TARGET_T1024RDB)
143 /* optimize cpo for erratum A-009942 */
144 popts->cpo_sample = 0x52;
148 #ifdef CONFIG_SYS_DDR_RAW_TIMING
149 /* 2GB discrete DDR4 MT40A512M8HX on T1023RDB */
150 dimm_params_t ddr_raw_timing = {
152 .rank_density = 0x80000000,
153 .capacity = 0x80000000,
154 .primary_sdram_width = 32,
156 .registered_dimm = 0,
161 .bank_group_bits = 2,
163 .burst_lengths_bitmask = 0x0c,
166 .caslat_x = 0x000DFA00,
179 .refresh_rate_ps = 7800000,
180 .dq_mapping[0] = 0x0,
181 .dq_mapping[1] = 0x0,
182 .dq_mapping[2] = 0x0,
183 .dq_mapping[3] = 0x0,
184 .dq_mapping[4] = 0x0,
185 .dq_mapping[5] = 0x0,
186 .dq_mapping[6] = 0x0,
187 .dq_mapping[7] = 0x0,
188 .dq_mapping[8] = 0x0,
189 .dq_mapping[9] = 0x0,
190 .dq_mapping[10] = 0x0,
191 .dq_mapping[11] = 0x0,
192 .dq_mapping[12] = 0x0,
193 .dq_mapping[13] = 0x0,
194 .dq_mapping[14] = 0x0,
195 .dq_mapping[15] = 0x0,
196 .dq_mapping[16] = 0x0,
197 .dq_mapping[17] = 0x0,
201 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
202 unsigned int controller_number,
203 unsigned int dimm_number)
205 const char dimm_model[] = "Fixed DDR4 on board";
207 if (((controller_number == 0) && (dimm_number == 0)) ||
208 ((controller_number == 1) && (dimm_number == 0))) {
209 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
210 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
211 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
218 #if defined(CONFIG_DEEP_SLEEP)
219 void board_mem_sleep_setup(void)
221 void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
223 /* does not provide HW signals for power management */
224 clrbits_8(cpld_base + 0x17, 0x40);
225 /* Disable MCKE isolation */
226 gpio_set_value(2, 0);
233 phys_size_t dram_size;
235 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
236 #ifndef CONFIG_SYS_DDR_RAW_TIMING
237 puts("Initializing....using SPD\n");
239 dram_size = fsl_ddr_sdram();
241 /* DDR has been initialised by first stage boot loader */
242 dram_size = fsl_ddr_sdram_size();
244 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
245 dram_size *= 0x100000;
247 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
251 gd->ram_size = dram_size;