2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/processor.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_law.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/fsl_portals.h>
18 #include <asm/fsl_liodn.h>
24 #include <fsl_dtsec.h>
25 #include <asm/fsl_serdes.h>
26 #include "../common/fman.h"
28 int board_eth_init(bd_t *bis)
30 #if defined(CONFIG_FMAN_ENET)
32 struct memac_mdio_info dtsec_mdio_info;
33 struct memac_mdio_info tgec_mdio_info;
35 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
38 srds_s1 = in_be32(&gur->rcwsr[4]) &
39 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
40 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
42 dtsec_mdio_info.regs =
43 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
45 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
47 /* Register the 1G MDIO bus */
48 fm_memac_mdio_init(bis, &dtsec_mdio_info);
51 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
52 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
54 /* Register the 10G MDIO bus */
55 fm_memac_mdio_init(bis, &tgec_mdio_info);
57 /* Set the on-board RGMII PHY address */
58 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
61 #ifdef CONFIG_T1024RDB
63 /* set the on-board RGMII2 PHY */
64 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
66 /* set 10G XFI with Aquantia AQR105 PHY */
67 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
74 /* set the on-board 2.5G SGMII AQR105 PHY */
75 fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
76 #ifdef CONFIG_T1023RDB
77 /* set the on-board 1G SGMII RTL8211F PHY */
78 fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
82 printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
87 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
88 interface = fm_info_get_enet_if(i);
90 case PHY_INTERFACE_MODE_RGMII:
91 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
92 fm_info_set_mdio(i, dev);
94 case PHY_INTERFACE_MODE_SGMII:
95 #if defined(CONFIG_T1023RDB)
96 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
97 #elif defined(CONFIG_T1024RDB)
98 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
100 fm_info_set_mdio(i, dev);
102 case PHY_INTERFACE_MODE_SGMII_2500:
103 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
104 fm_info_set_mdio(i, dev);
111 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
112 switch (fm_info_get_enet_if(i)) {
113 case PHY_INTERFACE_MODE_XGMII:
114 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
115 fm_info_set_mdio(i, dev);
123 #endif /* CONFIG_FMAN_ENET */
125 return pci_eth_init(bis);
128 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
129 enum fm_port port, int offset)
131 #if defined(CONFIG_T1024RDB)
132 if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
133 (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
134 (port == FM1_DTSEC3)) {
135 fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
136 fdt_setprop_string(fdt, offset, "phy-connection-type",
138 fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
143 void fdt_fixup_board_enet(void *fdt)