git.sur5r.net Git - u-boot/blob - board/freescale/t102xrdb/eth_t102xrdb.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <netdev.h>
  10 #include <asm/mmu.h>
  11 #include <asm/processor.h>
  12 #include <asm/immap_85xx.h>
  13 #include <asm/fsl_law.h>
  14 #include <asm/fsl_serdes.h>
  15 #include <asm/fsl_portals.h>
  16 #include <asm/fsl_liodn.h>
  17 #include <malloc.h>
  18 #include <fm_eth.h>
  19 #include <fsl_mdio.h>
  20 #include <miiphy.h>
  21 #include <phy.h>
  22 #include <asm/fsl_dtsec.h>
  23 #include <asm/fsl_serdes.h>
  24 #include "../common/fman.h"
  25
  26 int board_eth_init(bd_t *bis)
  27 {
  28 #if defined(CONFIG_FMAN_ENET)
  29         int i, interface;
  30         struct memac_mdio_info dtsec_mdio_info;
  31         struct memac_mdio_info tgec_mdio_info;
  32         struct mii_dev *dev;
  33         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  34         u32 srds_s1;
  35
  36         srds_s1 = in_be32(&gur->rcwsr[4]) &
  37                                         FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  38         srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  39
  40         dtsec_mdio_info.regs =
  41                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
  42
  43         dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  44
  45         /* Register the 1G MDIO bus */
  46         fm_memac_mdio_init(bis, &dtsec_mdio_info);
  47
  48         tgec_mdio_info.regs =
  49                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
  50         tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  51
  52         /* Register the 10G MDIO bus */
  53         fm_memac_mdio_init(bis, &tgec_mdio_info);
  54
  55         /* Set the on-board RGMII PHY address */
  56         fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
  57
  58         switch (srds_s1) {
  59         case 0x95:
  60                 /* set the on-board RGMII2  PHY */
  61                 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
  62
  63                 /* set 10G XFI with Aquantia AQR105 PHY */
  64                 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
  65                 break;
  66         case 0x77:
  67         case 0x135:
  68                 /* set the on-board 2.5G SGMII AQR105 PHY */
  69                 fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY1_ADDR);
  70                 break;
  71         default:
  72                 printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
  73                        srds_s1);
  74                 break;
  75         }
  76
  77         for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  78                 interface = fm_info_get_enet_if(i);
  79                 switch (interface) {
  80                 case PHY_INTERFACE_MODE_RGMII:
  81                         dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
  82                         fm_info_set_mdio(i, dev);
  83                         break;
  84                 case PHY_INTERFACE_MODE_SGMII_2500:
  85                         dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
  86                         fm_info_set_mdio(i, dev);
  87                         break;
  88                 default:
  89                         break;
  90                 }
  91         }
  92
  93         for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
  94                 switch (fm_info_get_enet_if(i)) {
  95                 case PHY_INTERFACE_MODE_XGMII:
  96                         dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
  97                         fm_info_set_mdio(i, dev);
  98                         break;
  99                 default:
 100                         break;
 101                 }
 102         }
 103
 104         cpu_eth_init(bis);
 105 #endif /* CONFIG_FMAN_ENET */
 106
 107         return pci_eth_init(bis);
 108 }
 109
 110 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 111                               enum fm_port port, int offset)
 112 {
 113         if ((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) &&
 114             (port == FM1_DTSEC3)) {
 115                 fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
 116                 fdt_setprop(fdt, offset, "phy-connection-type",
 117                             "sgmii-2500", 10);
 118                 fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
 119         }
 120 }
 121
 122 void fdt_fixup_board_enet(void *fdt)
 123 {
 124 }