2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/processor.h>
12 #include <asm/immap_85xx.h>
13 #include <asm/fsl_law.h>
14 #include <asm/fsl_serdes.h>
15 #include <asm/fsl_portals.h>
16 #include <asm/fsl_liodn.h>
22 #include <asm/fsl_dtsec.h>
23 #include <asm/fsl_serdes.h>
25 int board_eth_init(bd_t *bis)
27 #if defined(CONFIG_FMAN_ENET)
29 struct memac_mdio_info dtsec_mdio_info;
30 struct memac_mdio_info tgec_mdio_info;
32 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
35 srds_s1 = in_be32(&gur->rcwsr[4]) &
36 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
37 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
39 dtsec_mdio_info.regs =
40 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
42 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
44 /* Register the 1G MDIO bus */
45 fm_memac_mdio_init(bis, &dtsec_mdio_info);
48 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
49 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
51 /* Register the 10G MDIO bus */
52 fm_memac_mdio_init(bis, &tgec_mdio_info);
54 /* Set the two on-board RGMII PHY address */
55 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
56 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
60 /* 10G XFI with Aquantia PHY */
61 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
64 printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
69 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
70 interface = fm_info_get_enet_if(i);
72 case PHY_INTERFACE_MODE_RGMII:
73 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
74 fm_info_set_mdio(i, dev);
81 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
82 switch (fm_info_get_enet_if(i)) {
83 case PHY_INTERFACE_MODE_XGMII:
84 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
85 fm_info_set_mdio(i, dev);
93 #endif /* CONFIG_FMAN_ENET */
95 return pci_eth_init(bis);
98 void fdt_fixup_board_enet(void *fdt)