2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
13 #include <asm/processor.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_law.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/fsl_liodn.h>
20 #ifdef CONFIG_T1024RDB
22 #elif defined(CONFIG_T1023RDB)
26 #include "../common/sleep.h"
28 DECLARE_GLOBAL_DATA_PTR;
30 #ifdef CONFIG_T1023RDB
32 GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
34 GPIO3_GET_VERSION, /* GPIO3_4/5, 00:RevB, 01: RevC */
35 GPIO3_BRD_VER_MASK = 0x0c000000,
36 GPIO3_OFFSET = 0x2000,
45 struct cpu_type *cpu = gd->arch.cpu;
46 static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
47 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
50 srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
51 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
53 printf("Board: %sRDB, ", cpu->name);
54 #if defined(CONFIG_T1024RDB)
55 printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
56 CPLD_READ(hw_ver), CPLD_READ(sw_ver));
57 #elif defined(CONFIG_T1023RDB)
58 printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
66 #elif defined(CONFIG_T1024RDB)
69 reg = CPLD_READ(flash_csr);
71 if (reg & CPLD_BOOT_SEL) {
74 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
75 printf("NOR vBank%d\n", reg);
77 #elif defined(CONFIG_T1023RDB)
81 printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK));
85 puts("SERDES Reference Clocks:\n");
87 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
89 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);
94 #ifdef CONFIG_T1024RDB
95 static void board_mux_lane(void)
97 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
99 u8 reg = CPLD_READ(misc_ctl_status);
101 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
102 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
103 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
105 if (srds_prtcl_s1 == 0x95) {
106 /* Route Lane B to PCIE */
107 CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
109 /* Route Lane B to SGMII */
110 CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
112 CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
116 int board_early_init_f(void)
118 #if defined(CONFIG_DEEP_SLEEP)
120 fsl_dp_disable_console();
126 int board_early_init_r(void)
128 #ifdef CONFIG_SYS_FLASH_BASE
129 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
130 int flash_esel = find_tlb_idx((void *)flashbase, 1);
132 * Remap Boot flash region to caching-inhibited
133 * so that flash can be erased properly.
136 /* Flush d-cache and invalidate i-cache of any FLASH data */
139 if (flash_esel == -1) {
140 /* very unlikely unless something is messed up */
141 puts("Error: Could not find TLB for FLASH BASE\n");
142 flash_esel = 2; /* give our best effort to continue */
144 /* invalidate existing TLB entry for flash + promjet */
145 disable_tlb(flash_esel);
148 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
149 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
150 0, flash_esel, BOOKE_PAGESZ_256M, 1);
153 #ifdef CONFIG_T1024RDB
160 unsigned long get_board_sys_clk(void)
162 return CONFIG_SYS_CLK_FREQ;
165 unsigned long get_board_ddr_clk(void)
167 return CONFIG_DDR_CLK_FREQ;
170 int misc_init_r(void)
175 int ft_board_setup(void *blob, bd_t *bd)
180 ft_cpu_setup(blob, bd);
182 base = getenv_bootm_low();
183 size = getenv_bootm_size();
185 fdt_fixup_memory(blob, (u64)base, (u64)size);
188 pci_of_setup(blob, bd);
191 fdt_fixup_liodn(blob);
192 fsl_fdt_fixup_dr_usb(blob, bd);
194 #ifdef CONFIG_SYS_DPAA_FMAN
195 fdt_fixup_fman_ethernet(blob);
196 fdt_fixup_board_enet(blob);
199 #ifdef CONFIG_T1023RDB
200 if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
201 fdt_enable_nor(blob);
207 #ifdef CONFIG_T1023RDB
208 /* Enable NOR flash for RevC */
209 static void fdt_enable_nor(void *blob)
211 int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash");
214 fdt_status_okay(blob, nodeoff);
216 printf("WARNING unable to set status for NOR\n");
219 int board_mmc_getcd(struct mmc *mmc)
221 ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
222 u32 val = in_be32(&pgpio->gpdat);
224 /* GPIO1_14, 0: eMMC, 1: SD/MMC */
230 int board_mmc_getwp(struct mmc *mmc)
232 ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
233 u32 val = in_be32(&pgpio->gpdat);
240 static u32 t1023rdb_ctrl(u32 ctrl_type)
242 ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
243 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
244 u32 val, orig_bus = i2c_get_bus_num();
249 val = in_be32(&pgpio->gpdat);
251 out_be32(&pgpio->gpdat, val);
252 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
255 val = in_be32(&pgpio->gpdat);
256 val &= ~GPIO1_SD_SEL;
257 out_be32(&pgpio->gpdat, val);
258 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
260 case GPIO3_GET_VERSION:
261 pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
263 val = in_be32(&pgpio->gpdat);
264 val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
265 if (val == 0x3) /* GPIO3_4/5 not used on RevB */
269 i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
270 i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
272 tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
273 i2c_set_bus_num(orig_bus);
276 i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
278 i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
280 i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
281 /* asserting HRESET_REQ */
282 out_be32(&gur->rstcr, 0x2);
285 i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
287 i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
289 i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
290 out_be32(&gur->rstcr, 0x2);
298 static int switch_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
302 return CMD_RET_USAGE;
303 if (!strcmp(argv[1], "bank0"))
304 t1023rdb_ctrl(I2C_SET_BANK0);
305 else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank"))
306 t1023rdb_ctrl(I2C_SET_BANK4);
307 else if (!strcmp(argv[1], "sd"))
308 t1023rdb_ctrl(GPIO1_SD_SEL);
309 else if (!strcmp(argv[1], "emmc"))
310 t1023rdb_ctrl(GPIO1_EMMC_SEL);
312 return CMD_RET_USAGE;
317 switch, 2, 0, switch_cmd,
318 "for bank0/bank4/sd/emmc switch control in runtime",
319 "command (e.g. switch bank4)"